Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage
Reexamination Certificate
1999-11-11
2001-09-18
Kim, Jung Ho (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
With specific source of supply or bias voltage
C327S589000
Reexamination Certificate
active
06292048
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to the field of computers and computer systems. More particularly, the present invention relates to a gate enhancement charge pump for a low voltage power supply.
BACKGROUND OF THE INVENTION
Many of today's computing applications such as cellular phones, digital cameras, and personal computers, use nonvolatile memories to store data or code. Nonvolatility is advantageous because it allows the computing system to retain its data and code even when power is removed from the computing system. Thus if the system is turned off or if there is a power failure, there is no loss of code or data.
One example of a nonvolatile memory device is the flash Electrically Erasable Programmable Read-only Memory (flash EEPROM or flash memory). Flash memory can be programmed by the user, and once programmed, the flash memory retains its data until the memory is erased. Electrical erasure of the flash memory erases the contents of the memory of the device in one relatively rapid operation. The flash memory may then be programmed with new code or data.
Flash memories have been used in portable computers and similar circuitry as both read only memory and as long term storage which may be both read and written. However, the tendency has been to reduce the power requirements of such portable computers to make systems lighter and to increase the length of use between recharging. This has required that the voltage potentials available to program the flash memory arrays be reduced. Flash memories must be able to operate in systems where a VCC supply voltage of 5V, 3V, or an even smaller voltage is available to circuit components. However, performing program and erase operations in flash memory components requires that greater voltage than that supplied to the component be applied to the flash memory cells. For example, a program operation may require that approximately 10.5V be applied to a memory cell. In order to achieve this voltage, a charge pump circuit is required in the flash memory component. A positive charge pump can take a supplied VCC voltage and create a voltage sufficient for program operations. The charge pump must also be able to deliver sufficient current at the required voltage levels.
FIG. 1
is a typical implementation of a prior positive charge pump
100
. The charge pump
100
of
FIG. 1
is comprised of three pump stages. A number of N type field effect transistors N2
116
, N4
126
, N6
136
, N7
142
are coupled in series between a VCC supply source
110
and a pump output terminal VOUT
150
. Each stage of the pump
100
includes an N type device N1
112
, N3
122
, N5
132
to control the voltage potential at the gate terminal of the coupling transistor N2
116
, N4
126
, N6
136
of that respective stage. Each stage also includes a pump capacitor C1
114
, C3
124
, C5
134
and a boot capacitor C2
118
, C4
128
, C6
138
. Clock signals
1
and
3
are supplied to the circuit
100
from source 1
106
and source 3
108
, respectively, via capacitors C2
118
, C4
128
, C6
138
. Clock signals
2
and
4
are supplied from source 2
104
and source 4
102
, respectively, via capacitors C1
114
, C3
124
, C5
134
.
FIG. 2
shows a timing diagram of clock signals used in connection with the prior art charge pump circuit of FIG.
1
. In order to understand the operation of the circuit
100
, the operation of a single stage
190
including the switching transistor N4
126
will be discussed.
FIG. 2
shows the clock signals referred to as CLOCK 1
210
, CLOCK 2
220
, CLOCK 3
230
, and CLOCK 4
240
associated with the circuit
100
. Following the prior art timing diagram of
FIG. 2
, CLOCK 3
230
and CLOCK 4
240
are initially at a logic high level. Because CLOCK 3
230
is high, the pre-charge device N3
122
is initially on. When CLOCK 1
210
signal transitions to a logic high during time T1, the voltage pulse applied through C2
118
charges C3
124
on node
170
at the gate terminal of N4
126
through N3
122
. C3
124
is charged to the voltage level of the gate terminal of device N3
122
minus a threshold voltage drop. When CLOCK 3
230
transitions to a logic low, N3
122
turns off, isolating the gate of N4
126
and leaving C3
124
charged. This also lowers the voltage at the source terminal of N4
126
at node
130
such that N4
126
begins to conduct. When CLOCK 2
220
transitions to a logic high, the voltage at the gate of N4
126
is appreciably higher than at its drain terminal at node
120
because of the pre-charging of C3
124
. Hence N4
126
is turned on in the operating region where the device experiences no threshold voltage drop. The elimination of the threshold voltage drop means that the circuit
100
can provide increased current from C2
118
to the next stage. The high voltage at C2
118
begins to charge capacitor C4
128
and to discharge capacitor C5
134
through N5
132
.
As CLOCK 2
220
transitions low, N4
126
begins to turn off. When CLOCK 3
230
transitions high, N3
122
turns on to discharge the gate terminal of N4
126
and brings node
170
toward the voltage of the drain terminal so that N4
126
turns off. When CLOCK 1
210
goes low, N4
126
stays off and N3
122
stays on such that the charge at the drain and gate terminals of N4
126
are equalized.
Viewing the circuit
100
as a whole, when the device N2
116
comes on in response to a high CLOCK 4
240
, its gate terminal has been charged through N1
112
. Thus, N2
116
turns on without a threshold voltage drop and charges C2
118
rapidly. N2
116
begins to turns off as CLOCK 4
240
goes low. The rising CLOCK 1
210
pulse completes the turnoff of N2
116
by discharging C1
114
through N1
112
. The high CLOCK 1
210
continues the charging of C3
124
until the drop of CLOCK 3
230
. A low CLOCK 3
230
turns off N3
122
, leaving the gate terminal of N4
126
charged. The lowering of CLOCK 3
230
begins turning on N4
126
, which comes on completely without a threshold voltage drop when CLOCK 2
220
goes high and the voltage potential at the gate terminal of N4
126
rises above the potential at the drain terminal. This allows the charging of C4
128
. The same sequence continues through whatever number of stages are present in the pump
100
until the charge on the capacitor C6
138
of the final stage is sufficient to turn on N7
142
to provide a pumped voltage level at the output VOUT
150
. The last stage of the pump
100
operates in a range in which it experiences a threshold voltage drop.
In addition to experiencing a threshold voltage drop in the last stage, prior pump circuits such as that discussed above have the disadvantage of being unable to provide adequate current when required to operate with supply voltages below approximately 3V. For example, the pump circuit
100
discussed above would be unable to produce adequate current when supplied with 1.8V and pumping up to a voltage of 10.5V. An analogous situation exists with prior negative charge pumps, where a negative pump may need to pump to a voltage of approximately −12.5 when a supply voltage of 1.8V is supplied.
SUMMARY OF THE INVENTION
A gate enhancement charge pump for a low voltage power supply is described. The charge pump stage circuit comprises a first transistor comprising a first terminal, a second terminal, and a third terminal. The stage further comprises a first capacitor comprising a first terminal coupled to a first clock source and a second terminal coupled to said third terminal of said first transistor. The circuit also comprises a second capacitor comprising a first terminal coupled to a second clock source and a second terminal coupled to said second terminal of said first transistor. The circuit further comprises a first diode comprising an input terminal coupled to said first terminal of said first transistor and an output terminal coupled to said second terminal of said first transistor. The circuit also comprises a second diode comprising a control terminal coupled to a control device, an inp
Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
Kim Jung Ho
LandOfFree
Gate enhancement charge pump for low voltage power supply does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Gate enhancement charge pump for low voltage power supply, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Gate enhancement charge pump for low voltage power supply will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2536693