Gate electrode formation method

Details Gate electrode formation method Gate electrode formation method

1999-10-21

2001-04-17

Ramsey, Kenneth J. (Department: 2879)

Electric lamp or space discharge component or device manufacturi

Process

With assembly or disassembly

Reexamination Certificate

active

06217403

ABSTRACT:

FIELD OF THE INVENTION
The present claimed invention relates to the field of flat panel displays. More particularly, the present claimed invention relates to the formation of a gate electrode for a flat panel display screen structure.
BACKGROUND ART
In certain flat panel display devices such as, for example, flat display devices utilizing cold cathodes, a gate electrode is required. In such flat panel display devices, an electron emissive cold cathode is disposed between a first electrode (e.g. a row electrode) and a second electrode (e.g. a gate electrode). By generating a sufficient voltage potential between the row electrode and the gate electrode, the electron emissive cold cathode is caused to emit electrons. In one approach, the emitted electrons are accelerated, through openings in the gate electrode, towards a display screen. In such flat panel display devices, it is desirable to have the openings uniformly and consistently arranged with sufficient spacing provided between each opening to avoid overlapping in the gate electrode.
With reference now to Prior Art
FIG. 1
, a side sectional view of a conventional process step used in the formation of a prior art gate electrode is shown. As shown in Prior Art
FIG. 1
, a first electrode
102
has an insulating layer
104
disposed thereon. In a conventional gate electrode formation process, a non-insulating material is deposited on top of insulating layer
104
to form a very thin non-insulating layer
106
(e.g. on the order of 100 angstroms) of the non-insulating material.
With reference now to Prior Art
FIG. 2
, conventional gate electrode formation processes then deposit spheres, typically shown as
108
, onto very thin non-insulating layer
106
. Because layer
106
is very thin, it is extremely difficult for such prior art gate electrode formation processes to make very thin non-insulating layer
106
continuous. As a result, spheres
108
are not uniformly or consistently deposited across the surface of very thin non-insulating layer
106
in conventional gate electrode formation processes.
With reference next to Prior Art
FIG. 3
, a second layer of non-insulating material
110
is then deposited over the very thin non-insulating layer
106
and over spheres
108
. As shown in Prior Art
FIG. 3
, second layer of non-insulating material
110
is much thicker than very thin layer of non-insulating material
106
. In such prior art approaches, very thin non-insulating layer
106
together with second non-insulating layer
110
comprise the body of the gate electrode.
As shown in Prior Art
FIG. 4
, after the deposition of second non-insulating layer
110
, spheres
108
and portions of second non-insulating layer
110
which overlie spheres
108
are removed. As a result, regions, typically shown as
112
, of very thin non-insulating layer
106
have second non-insulating layer
110
removed therefrom.
Referring still to Prior Art
FIG. 4
, after the removal of spheres
108
and portions of second non-insulating layer
110
which overlie spheres
108
, an etch step is performed. The etch step is used to form openings through very thin non-insulating layer
106
. As mentioned above, spheres
108
are not uniformly or consistently disposed across the surface of very thin non-insulating layer
106
in conventional gate electrode formation processes. Consequently, conventionally formed openings in second non-insulating layer
110
and very thin non-insulating layer
106
are likewise not uniformly or consistently disposed across the surface of very thin non-insulating layer
106
. In addition to forming openings through second non-insulating layer
110
and very thin non-insulating layer
106
, the etch step of conventional gate electrode formation processes also substantially etches second non-insulating layer
110
. The etching of second non-insulating layer
110
reduces the thickness thereof. Therefore, second non-insulating layer
110
must be deposited to a thickness which is greater than the desired thickness of the gate electrode, so that second non-insulating layer
110
will be of the desired thickness after being subjected to the etch environment. Thus, conventional gate electrode formation processes reduce the thickness of the gate electrode across the entire surface thereof when etching openings through the gate electrode, as shown in Prior Art FIG.
5
.
Referring again to Prior Art
FIG. 5
, as yet another drawback, during etch steps of the above-described gate electrode formation process, the top surface of second non-insulating layer
110
is subjected to the etch environment. In addition to reducing the thickness of second insulating layer
110
, the etch environment induces deleterious effects such as, for example, oxidation at the top surface of second non-insulating layer
110
. Oxidation of the top surface of second non-insulating layer
110
complicates other processes such as the removal of subsequently deposited emitter material. Thus, conventional gate electrode formation processes subject the gate electrode to unwanted etching, and degrade the surface integrity of the gate electrode.
As still another drawback, thickness uniformity of the gate film remaining after an etch process crucially depends on the etch uniformity of the etch system employed. In large area panels, such etch non-uniformity is a major concern, because it is extremely difficult to achieve sufficient etch uniformity across the large area panels. The problem of etch non-uniformity is further exacerbated when etching through submicron features.
Thus, a need exists for a gate electrode formation method which provides for improved spacing of openings formed through the gate electrode. Another need exists for a gate electrode formation process which does not reduce the thickness of the gate electrode across the entire surface thereof when etching openings through the gate electrode. Yet another need exists for a method which provides a gate electrode having good surface integrity and an undamaged top surface after the formation thereof.
SUMMARY OF INVENTION
The present invention is comprised of a method which provides for improved spacing of openings formed through the gate electrode. The present invention further comprises a method which does not reduce the thickness of the gate electrode across the entire surface thereof when etching openings through the gate electrode. The present invention also provides a gate electrode having good surface integrity and an undamaged top surface after the formation thereof.
Specifically, in one embodiment, the present invention comprises depositing a gate metal over an underlying substrate such that a layer of the gate metal is formed above the underlying substrate. In the present invention, the layer of the gate metal is deposited to a thickness approximately the same as the thickness desired for the gate electrode. Next, the present invention deposits polymer particles uniformly and consistently arranged onto the layer of gate metal. A sacrificial hard mask layer is then deposited over the polymer particles and the layer of the gate metal. In the present invention, the sacrificial hard mask layer is comprised of a material which is not adversely affected/substantially etched during the etching of the gate metal. The present invention removes the polymer particles and portions of the hard mask layer which overlie the polymer particles such that first regions of the layer of the gate metal are exposed, and such that second regions of the layer of the gate metal remain covered by the hard mask layer. After the removal step, the present invention etches through the first regions of the layer of the gate metal such that openings are formed completely through the layer of the gate metal at the first regions. After the openings have been formed, the present invention then removes the remaining portions of the hard mask layer which overlie the second regions of the layer of the gate metal.
In one embodiment, the gate metal is comprised of chromium. In such an embodiment, the present invention etches th

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