Gate edge aligned EEPROM transistor

Details Gate edge aligned EEPROM transistor Gate edge aligned EEPROM transistor

1996-09-30

1998-11-17

Nguyen, Viet Q.

Static information storage and retrieval

Floating gate

Particular connection

3651851, 36518526, 36518528, 257321, 257316, H01L 29788, G11C 1300

Patent

active

058386165

ABSTRACT:
An electrically-erasable electrically-programmable read only memory (EEPROM) transistor is programmed and erased by electron tunneling and reduces gate induced drain leakage. The EEPROM transistor comprises a semiconductor substrate having source and drain regions disposed horizontally apart. A floating gate conductor is vertically adjacent to and spaced from the source and drain regions. An insulation layer is disposed between the floating gate conductor and the source and drain regions. A first segment of the insulation layer, which is between the drain region and a minor portion of the floating gate conductor, has a first thickness. A second segment of the insulation layer which is adjacent to the first layer and the remainder on the floating gate conductor, has a second thickness which is substantially greater than the first thickness. A low density diffusion area is defined within a segment of the semiconductor substrate which extends from the drain region, encompasses the first segment of the insulation layer, to underneath a portion of the second segment of the insulation layer.

REFERENCES:
patent: 4132904 (1979-01-01), Harari
patent: 4663645 (1987-05-01), Komori et al.
patent: 4775642 (1988-10-01), Chang et al.
patent: 4788663 (1988-11-01), Tanaka et al.
patent: 4918501 (1990-04-01), Komori et al.
patent: 4935802 (1990-06-01), Noguchi et al.
patent: 4972371 (1990-11-01), Komori et al.
patent: 5065362 (1991-11-01), Herdt et al.
patent: 5095344 (1992-03-01), Harari
patent: 5098855 (1992-03-01), Komori et al.
patent: 5153144 (1992-10-01), Komori et al.
patent: 5172200 (1992-12-01), Muragishi et al.
patent: 5172338 (1992-12-01), Mehrotra et al.
patent: 5189640 (1993-02-01), Hurard
patent: 5194924 (1993-03-01), Komori
patent: 5220533 (1993-06-01), Turner
patent: 5241498 (1993-08-01), Yokokura
patent: 5267209 (1993-11-01), Yoshida
patent: 5278794 (1994-01-01), Tanaka et al.
patent: 5280446 (1994-01-01), Ma et al.
patent: 5283759 (1994-02-01), Smith
patent: 5299162 (1994-03-01), Kim et al.
patent: 5352620 (1994-10-01), Komori et al.
patent: 5353248 (1994-10-01), Gupta
patent: 5355007 (1994-10-01), Smayling
patent: 5361224 (1994-11-01), Takasu
patent: 5373465 (1994-12-01), Chen et al.
patent: 5386422 (1995-01-01), Endoh et al.
patent: 5399917 (1995-03-01), Allen et al.
patent: 5412238 (1995-05-01), Chang
patent: 5453388 (1995-09-01), Chen et al.
patent: 5455790 (1995-10-01), Hart et al.
patent: 5460998 (1995-10-01), Liu
patent: 5552621 (1996-09-01), Kowalski
patent: 5661687 (1997-08-01), Randazzo

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