Gate drive circuit with feedback-controlled active resistance

Details Gate drive circuit with feedback-controlled active resistance Gate drive circuit with feedback-controlled active resistance

2001-10-23

2002-10-01

Nuton, My-Trang (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Gating

Signal transmission integrity or spurious noise override

C327S380000

Reexamination Certificate

active

06459324

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a gate drive circuit with a feedback-controlled active resistance. More specifically, the invention relates to a gate drive circuit that modifies the turn-on and turn-off steps in a drive signal to reduce di/dt and therefore electromagnetic interference, particularly for insulated gate devices.
2. Brief Description of the Related Art
Power switches used in power converters are usually insulated gate devices such as insulated gate bipolar transistors (IGBTs). These devices need a special control circuit to provide signals to their gates, usually called a gate driver. Typically, a gate driver has a simple structure that allows application of either positive or negative voltage on the gate.
A. Switching Waveforms
FIG. 1
shows typical switching waveforms that occur at turn-on in an insulated gate device. The waveforms illustrate the slopes of the collector voltage and current and the time intervals on which di/dt (&dgr;
1
) and dv/dt (&dgr;
2
) are defined.
During the &dgr;
0
time interval, the gate voltage (V
G
) rises to the threshold level and the collector current I
C
) equals I
dss
up to hundreds of &mgr;A. The slope of the gate voltage is given by the input capacitance that is now equal to C
iss
for the specific device.
During the &dgr;
1
time interval, I
C
starts to increase and reaches its maximum equal to the load current. The slope at which I
C
increases depends on the gate resistance (R
GON
) and IGBT characteristics. An approximate equation is:
(
ⅆ
i
d
ⅆ
t
)
on
≈
V
G
+
-
V
GE
⁡
(
I
L
+
I
RM
)
(
C
ies
·
R
GON
g
fe
)
+
L
E
(
1
)
During the &dgr;
2
time interval, the Miller effect interval keeps the gate voltage at a constant level while the collector-emitter voltage decreases from the DC bus level. The slope of this variation also depends on the gate resistance and is given by an approximate relationship:
(
ⅆ
v
ⅆ
t
)
on
≈
V
G
+
-
V
GE
⁡
(
I
C
)
R
Gon
·
C
GC
(
2
)
During the &dgr;
3
time interval, the gate voltage again increases to the control voltage.
FIG. 2
shows typical switching waveforms that occur at turn-off. As above, the waveforms illustrate current and voltage slopes.
During the &dgr;
0
′ time interval, the gate voltage (V
G
) decreases up to the Miller effect level.
During the &dgr;
1
′ time interval, the collector-emitter voltage increases to the DC bus voltage and the slope is defined by the gate resistance and the IGBT's characteristics. The slope is given by another approximate relationship:
(
ⅆ
v
ⅆ
t
)
off
≈
V
GE
⁡
(
I
L
)
-
V
Gmin
R
Goff
·
C
GC
(
3
)
During the &dgr;
2
′ time interval, the collector current decreases and the slope is approximated by an equation similar to equation (1) above.
B. Influence on EMI
The design of a gate driver has an important influence on the EMI that is generated. It can influence both major types of electromagnetic interference:
differential mode currents flowing into connecting lines due to the IGBT's/diode's switching current (di/dt); and
common mode interference produced by the high rate of change of the switching voltage (dv/dt) and parasitic capacitances to the ground or connecting lines.
The level of radiated or conducted EMI depends not only on the gate resistance but also in the converter system parasitics and the pulse width modulation (PWM) method being used.
To control EMI emission, it is necessary to control the switching rate and the voltage and current waveforms based on the values of gate resistance and the switching off voltage (−15V or 0V). For a typical inverter, problems with differential mode EMI constrain the designer to reduce di/dt. The dv/dt levels are imposed by output waveform harmonic considerations and cannot be reduced very much. The harmonic content of the output voltage and switching loss considerations make it impossible to slow down the switching speed. On the contrary, fast dv/dt inverters are sometimes desirable. Recently developed approaches make it possible to control di/dt without affecting dv/dt capability by injecting additional gate current when necessary. Usually designers use such controls to reduce turn-on di/dt and to reduce overvoltage at turn-off.
Gate resistor design is subject to other constraints such as switching power losses, diode recovery transients, and the need to avoid cross-conduction. As used herein, the term “gate resistor” refers to a gate resistor equivalent that can be implemented by various means including, but not limited to, a conventional passive resistor.
Circuit
20
in
FIG. 3
illustrates a simplified approach to controlling (di/dt) by controlling gate current with a proposed feedback loop from the emitter of IGBT
22
to the output of gate driver
24
. This approach is described in detail in Gerster, C., and Hofer-Noser, P., “Gate-controlled dv/dt and di/dt Limitation in High-Power IGBT Converters,”
EPE Journal
, Vol. 5, No. 3/4, January 1996.
There are numerous obvious constraints on implementing this approach, and a number of different solutions have been proposed by those seeking the best implementation. Two main constraints preventing easy implementation are:
a fast event time scale that allows very little delay within the circuit; and
feedback dependence on IGBT parameters.
The literature presents many solutions, based on different understandings of the problem. EMI generation is not simple to quantify, and its real sources and their weights in overall EMI generation are not easy to identify. Every possible parasitic in the inverter setup has an influence, and both di/dt and dv/dt contribute through the parasitics, during both turn-on and turn-off.
C. Solution I
Musumeci, S., Raciti, A., Testa, A., Galluzzo, A., and Melito, M., “Switching Behavior Improvement of Insulated Gate-Controlled Devices”,
IEEE Trans. On PE
, Vol. 12, No. 4, July 1997, pp. 645-653, propose a solution that shapes gate current during the Miller effect interval. This achieves independent control of the slopes of collector voltage and current. The proposed solution, illustrated by circuit
30
in
FIG. 4
, supplies pulses of gate current to IGBT
32
at the beginning of the Miller effect interval, speeding up the variation of the collector voltage without changing the slope of the collector current. Problems with this solution relate to detection of the Miller effect zone by sensor
34
and enabling a suitable current pulse generator
36
synchronous with the moment the zone is reached. This is very important to minimize power losses. Maximum loss reduction has been demonstrated by inserting gate current pulses within 20% delay after sensing the Miller effect zone. This can be achieved by an optimal gate-emitter voltage, a strong constant current pulse from generator
36
at turn-on, and a constant current sink
38
at turn-off.
Among the most sensitive parts of this design is implementation of enable modules
40
and
42
. The simplest solution is a high gain amplifier that converts information from sensor
34
into signals that, for example, cause generator
36
to provide gate current pulses. The main drawbacks of this solution relate to dependence on circuit speed and to noise. A more complex solution employs a phase locked loop (PLL) circuit to synchronize current pulses on a next-pulse basis. The PLL circuit works to compensate any processing delay. Any phase difference detected by the phase comparator modifies time delay between command signal and gate current pulses, adjusting the phase difference on the next switching.
FIGS. 5 and 6
show examples of relationships between V
GE
in IGBT
32
and enable signals to current pulse generator
36
and current sink
38
, respectively.
D. Solution II
Takizawi, S., Igarashi, S., and Kuroki, K., “A New di/dt Control Gate Drive Circuit for IGBTs to Reduce EMI Noise and Switching Losses”,
IEEE
1998, pp. 1443-1449, propose another solution, a “di/dt suppressor”, that limits di/dt at turn-on if collecto

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