Data processing: structural design – modeling – simulation – and em – Simulating nonelectrical device or system
Reexamination Certificate
1997-08-20
2003-01-21
Jones, Hugh M. (Department: 2123)
Data processing: structural design, modeling, simulation, and em
Simulating nonelectrical device or system
C703S002000, C703S013000
Reexamination Certificate
active
06510404
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an apparatus and a method for calculating gate delay used in logic simulation and timing analysis, and in particular, to an apparatus and a method for calculating gate delay using an RC model.
2. Description of the Background Art
Recently, the higher integration and multifunction of a semiconductor integrated circuit are increasing its circuit scale, thereby making the time required for its development longer. One method of reducing the time required for the development is to minimize re-designing and re-development due to the malfunction of a produced semiconductor integrated circuit. To achieve this goal, the simulation result obtained in a stage of designing a semiconductor integrated circuit must approximate to the timing of a signal between the gates within an actually produced semiconductor integrated circuit, and therefore there is an increasing need for a delay calculation apparatus with higher accuracy.
FIG. 1
is a block diagram showing a structure of a conventional delay calculation apparatus. The delay calculation apparatus includes: an input waveform gradient calculation apparatus
51
for extracting the gradient of the input waveform applied to an input terminal of a gate; an output load model calculation apparatus
52
for RC modeling the load applied to an output terminal of the gate; a gate delay calculation apparatus
53
for calculating the delay experienced from the input terminal to the output terminal of the gate; and a wire delay calculation apparatus
54
for calculating the delay (due to wiring) between the output terminal of the gate and the input terminal of a gate in a next stage. Gate delay data
55
calculated by gate delay calculation apparatus
53
and wire delay data
56
calculated by wire delay calculation apparatus
54
are used in logic simulation or timing analysis by a simulator or the like.
FIG. 2
is a schematic diagram showing an example of a circuit in which delay calculation apparatus calculates gate delay data
55
and wire delay data
56
. The circuit includes gates (inverters)
41
-
44
and wires
45
-
50
between the gates. The processing procedure of delay calculation apparatus will now be described with reference to the circuit diagram shown in FIG.
2
.
The delay in a logic circuit is generally calculated from the delay of gates per se (gate delay data
55
) and the delay resulting from the wire capacitance between gates (wire delay data
56
). Therefore, calculation of gate delay data
55
and wire delay data
56
(on the side of the output terminal of a gate) for every gate by delay calculation apparatus enables logic simulation and timing analysis by a simulator or the like. For example, assume that delay calculation apparatus calculates the delay for gate
42
shown in FIG.
2
. First, input waveform gradient calculation apparatus
51
calculates the gradient amount of the voltage waveform applied to the input terminal of gate
42
based on the calculation result (gate delay data and wire delay data) of gate
41
in a preceding stage.
Wires
48
-
50
which carry the output voltage of gate
42
and the input of gates
43
and
44
are modeled by output load model calculation apparatus
52
. This modeling will be described later.
Gate delay calculation apparatus
53
receives the amount of input waveform gradient calculated by input waveform gradient calculation apparatus
51
and the output load model calculated by output load model calculation apparatus
52
, and calculates the gate delay between the input terminal and the output terminal of gate
42
to produce gate delay data
55
. Gate delay calculation apparatus
53
also calculates the gradient of the output voltage waveform in gate
42
and transmits it to wire delay calculation apparatus
54
.
Wire delay calculation apparatus
54
receives the output voltage waveform of gate
42
calculated by gate delay calculation apparatus
53
and the output load model calculated by output load model calculation apparatus
52
and calculates the wire delay between the output terminal of gate
42
and the input terminals of gates
43
and
44
to produce wire delay data
56
.
FIG. 3
is a block. diagram showing in further detail a structure of gate delay calculation apparatus
53
in FIG.
1
. Gate delay calculation apparatus
53
includes: an R
s
, T
o
parameter storage file
57
for storing a resistance value R
s
of source resistance and a fixed delay time T
o
; an R
s
, T
o
determination portion
58
for determining R
s
and T
o
which are required in gate delay calculation using parameters stored in R
s
, T
o
parameter storage file
57
; a gate delay determination portion
59
for calculating gate delay using R
s
and T
o
; and an input waveform determination portion
60
for calculating input waveform data
63
which is required for the calculation of wire delay by wire delay calculation apparatus
54
. The amount of input waveform gradient
61
and an output load model
62
indicate the value calculated by input waveform gradient calculation apparatus
51
and that calculated by output load model calculation apparatus
52
, respectively.
FIG. 4
is a diagram showing a structure of a &pgr; type RC model generally used as output load model
62
. The &pgr; type RC model includes a source resistance
71
of a gate, a switch
72
for connecting the output terminal of the gate to a &pgr; type load, and a &pgr; type load consisting of capacitance elements
74
and
75
and a resistance element
73
.
The processing procedure of gate delay calculation apparatus
53
will now be described with reference to a circuit diagram of a &pgr; type RC model shown in FIG.
4
.
R
s
, T
o
determination portion
58
determines resistance value R
s
, of source resistance
71
and fixed time delay T
o
from the parameters stored in R
s
, T
o
parameter storage file
57
, the amount of input waveform gradient
61
and output load model
62
. Fixed delay time T
o
represents the time at which switch
72
is turned from off to on and is significantly influenced by the amount of input waveform gradient
61
. Therefore, fixed delay time T
o
is set as a parameter so that it can be determined from the amount of input waveform gradient
61
and stored in R
s
, T
o
parameter storage file
57
. It is noted that while resistance value R
s
may be defined as a constant value independent of input and output states, it can also be set as a parameter in consideration of the amount of input waveform gradient
61
and output load model
62
to achieve the higher calculation accuracy of the gate delay. In this case, output load model
62
is referenced. Thus, with reference to the amount of input waveform gradient
61
, output load model
62
and the parameters stored in R
s
, T
o
parameter storage file
57
, R
s
, T
o
determination portion
58
determines the resistance value R
s
of source resistance and the value of fixed delay time T
o
.
It is noted that R
s
, T
o
parameter varies depending on a gate type and rising/falling of output, and therefore it is set as a parameter in accordance with the gate type and the change in direction of output. In addition, rising of a gate means a state in which a power supply is connected to the upper terminal of source resistance
71
of &pgr; type RC model shown in
FIG. 4
, whereas falling means a state in which the upper terminal of source resistance
71
is grounded. Gate delay is calculated by gate delay determination portion
59
using resistance value R
s
and fixed delay time T
o
determined by R
s
, T
o
determination portion
58
and output load model
62
. Gate delay is calculated by analyzing &pgr; type RC model shown in FIG.
4
. The resistance value R of resistance element
73
of &pgr; type RC model and the capacitance values C
1
and C
2
of capacitance elements
74
and
75
are determined from output load model
62
calculated by output load model calculation apparatus
52
. In modeling the output load of gate
42
in
FIG. 2
, for example, capacitance values C
1
Komoda Michio
Kuriyama Shigeru
Jones Hugh M.
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
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