Gate-coupled structure for enhanced ESD input/output pad protect

Details Gate-coupled structure for enhanced ESD input/output pad protect Gate-coupled structure for enhanced ESD input/output pad protect

1999-01-25

2000-10-03

Jackson, Stephen W.

Electricity: electrical systems and devices

Safety and protection of systems and devices

Load shunting by fault responsive means

361111, 361119, H02H 900

Patent

active

061281719

ABSTRACT:
An electrostatic discharge protection circuit comprising a static discharge input node, a first NMOS FET having its drain connected to the input node and its source and substrate connected to Vss, a first switch apparatus comprised of a first PMOS FET and a second NMOS FET having the source and substrate of the first PMOS FET connected to the input node, the drain and substrate of the second NMOS FET connected to Vss, the drain of the first PMOS FET connected at a junction to the drain of the second NMOS FET, and the gates of the first PMOS FET and of the second NMOS FET connected to Vdd and the junction connected to the gate of the first NMOS FET.

REFERENCES:
patent: 5910874 (1999-06-01), Iniewski et al.

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