Gate coupled SCR for ESD protection circuits

Details Gate coupled SCR for ESD protection circuits Gate coupled SCR for ESD protection circuits

1994-09-07

1999-05-25

Gaffin, Jeffrey A.

Electricity: electrical systems and devices

Safety and protection of systems and devices

Load shunting by fault responsive means

361111, H02H 900

Patent

active

059074620

ABSTRACT:
A protection device comprising a gate-coupled silicon-controlled rectifier (SCR) (100), SCR (100) comprises an anode (105) formed in n-well (104) and connected to a pad (128) and a cathode (111) connected to ground. A gate-coupled NMOS transistor (120) has a gate (116) connected through a resistive element (118) to ground. A n+ region (112) forms both the cathode (111) and a source of the NMOS transistor (120). N-well (104) forms the drain. Stress voltage is coupled from pad (128) to gate electrode (116) causing NMOS transistor (120) to conduct. This, in turn, triggers SCR (100) which dissipates the stress current at the pad (128). The coupled voltage at gate electrode (116) dissipates within a designed time constant through resistive element (118).

REFERENCES:
patent: 3891866 (1975-06-01), Okuhara et al.
patent: 4400711 (1983-08-01), Avery
patent: 4567500 (1986-01-01), Avery
patent: 4633283 (1986-12-01), Avery
patent: 4739438 (1988-04-01), Sato
patent: 4896243 (1990-01-01), Chatterjee et al.
patent: 4939616 (1990-07-01), Roundtree
patent: 5072273 (1991-12-01), Avery
patent: 5144517 (1992-09-01), Wieth
patent: 5225702 (1993-07-01), Chatterjee
patent: 5274262 (1993-12-01), Avery
patent: 5359211 (1994-10-01), Croft
patent: 5400202 (1995-03-01), Metz et al.
patent: 5528188 (1996-06-01), Au et al.
Amitava Chatterjee and Thomas Polgreen, "A Low-Voltage Triggering SCR For On-Chip ESD Protection at Output and Input Pads", 1990 Symposiium on VLSI Technology, pp. 75-76. No Month.
Amitava Chatterjee and Thomas Polgreen, "A Low-Voltage Triggering SCR For On-Chip ESD Protection at Output and Input Pads", IEEE Electron Devices Letters, vol. 12, No. 1, Jan. 1991, pp. 21-22.
Ajith Amerasekera and Amitava Chatterjee, "An Investigation of BiCMOS ESD Protection Circuit Elements and Applications in Submicron Technologies", EOS/ESD Symposium 92-265, p. 5B.6.1. Sep. 1992.
L.R. Avery, "Using SCR's As Transient Protection Structures in Integrated Circuits", EOS/ESD 1983, pp. 177-180. No Month.

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