Gate-coupled field-effect transistor pair amplifier

Details Gate-coupled field-effect transistor pair amplifier Gate-coupled field-effect transistor pair amplifier

1982-12-20

1985-05-21

Mullins, James B.

Amplifiers

With semiconductor amplifying device

Including differential amplifier

330277, 330288, H03F 316, H03F 345

Patent

active

045189269

ABSTRACT:
An enhancement mode (104, 204, 404) and a depletion mode (102, 202, 402) pair of N-channel MOS transistors have their drain-source conduction paths connected in series and provided with a bias current means (120, 220, 306, 410). The gates (106, 206, 308, 310) are coupled together as an input node. In one embodiment (100) their bulk regions are source-connected and the output (118) is from the source of the enhancement mode device (104) to obtain a source follower configuration amplifier. In a second embodiment (200), the output (218) is taken from the drain (208) of the depletion mode device (202) to obtain a common source configuration amplifier. Two source follower pairs (302, 304) are disclosed connected in parallel to form a differential input voltage amplifier stage (300). A common source pair (402, 404) is disclosed in combination with an additional enhancement mode transistor (406) to form a current mirror (400).

REFERENCES:
patent: 3509375 (1970-04-01), Gormley
patent: 4042839 (1977-08-01), Araki
patent: 4069431 (1978-01-01), Kucharewski
patent: 4443715 (1984-04-01), Fox

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