Active solid-state devices (e.g. – transistors – solid-state diode – Regenerative type switching device – Combined with field effect transistor
Reexamination Certificate
1999-03-30
2001-11-06
Jackson, Jr., Jerome (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Regenerative type switching device
Combined with field effect transistor
C257S139000, C257S141000, C257S152000, C257S156000, C257S162000
Reexamination Certificate
active
06313485
ABSTRACT:
BACKGROUND OF THE INVENTION
FIELD OF THE INVENTION
The present invention concerns a gate-controlled thyristor, such as a cascode-MOS thyristor in which an insulated gate bipolar transistor (IGBT) in a first cell and a thyristor in a main cell are connected together in such a way that the first cell and the main cell form a lateral FET with a channel of a first conductivity type.
Such a cascode MOS thyristor was already proposed many years ago in Published, Non-Prosecuted German Patent Application DE 30 24 015 A, corresponding to U.S. Pat. No. 4,502,070, and has recently been discussed again as a MOS controlled cascode thyristor (MCCT) (see the report “1200 V MCCT: A New Concept Three Terminal MOS-Gated Thyristor” by N. Iwamuro, T. Iwaana, Y. Harada and Y. Seki at the ISPSD 97 Conference). Such a cascode MOS thyristor, as well as general MOS-controlled bipolar structures, such as IGBTs and MOS Controlled Thyristors (MCTs), are preferred to MOSFETs because of their relatively low start-up resistance. As it is well known, generally speaking, switches should close at as high a voltage as possible, but when they are turned on or are conducting, they should have as low resistance as possible.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a gate-controlled thyristor that overcomes the above-mentioned disadvantages of the prior art devices of this general type, which is characterized by an especially low start-up resistance.
With the foregoing and other objects in view there is provided, in accordance with the invention, a gate-controlled thyristor, including: a first cell having a insulated gate bi-polar transistor (IGBT); and a main cell having a thyristor with an emitter zone and a layer embedded in the emitter zone of the thyristor for increasing charge carrier recombination, the thyristor connected to the IGBT such that the first cell and the main cell form a lateral field effect transistor (FET) having a channel of a first conducting type.
In order to create a gate-controlled thyristor, which is characterized by an especially low start-up resistance, it is proposed that, in a cascode MOS thyristor of the type mentioned at the outset, an additional layer be embedded in the emitter zone of the transistor, which increases the current carrier recombination. The additional layer can consist of a metal or silicide, for example, aluminum, titanium silicide, etc. Besides, in addition to the main cell, a second cell may also be connected with a MOS switch, which forms with the main cell a FET with a channel of a second conductivity type.
In the case of a positive gate voltage (see FIG.
8
), the thyristor cathode is grounded, so that the on-state DC resistance is extremely low. If zero volts or a negative gate voltage is applied, then the first cell is disconnected as a lateral and vertical FET (field-effect transistor), while the second cell conducts, for example, as a p-channel FET and no current flows.
The individual cells can be disposed next to one another in the striated form. It is also possible to dispose the first cell and the second cell concentrically around the main cell. The dimensions for the cells can be chosen arbitrarily, and it is also possible to provide only the first cell together with the main cell.
Optionally, an insulator layer can be disposed under the first cell and the second cell, which ensures better flooding, especially of the n-conducting base zone with charge carriers and as a result ensuring an even smaller start-up resistance. Optionally, the insulator layer can reach all the way to the p-conducting base zone of the thyristor or the main cell. In this case, when the insulator layer reaches the p-conducting base zone, an opening should be present in it in order to increase the effect of the IGBT.
An advantage of the present invention consists in the fact that a gate-controlled thyristor can be created, the FETs of which can be configured practically in any arbitrary way so that they can be adapted to the most varied applications.
For this purpose, at least one trench is made in the lateral FET where an insulated gate electrode is provided. Advantageously, at least one trench with a gate electrode is also applied in a FET of a second cell.
The gate-controlled thyristor according to the invention can be produced simply with the usual process procedures and is superior even to the existing cascode MOS thyristor with regard to conductivity, because they have a large channel surface formed by the side-wall FETs located in the trenches.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a gate-controlled thyristor, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
REFERENCES:
patent: 4007474 (1977-02-01), Yagi et al.
patent: 4502070 (1985-02-01), Leipold et al.
patent: 4982258 (1991-01-01), Baliga
patent: 5124772 (1992-06-01), Hideshima
patent: 5162876 (1992-11-01), Kitagawa
patent: 5262336 (1993-11-01), Pike
patent: 5306930 (1994-04-01), Baliga
patent: 5608235 (1997-03-01), Pezzani
patent: 30 24 015 A1 (1982-01-01), None
patent: 38 42 468 C2 (1989-06-01), None
patent: 0 043 009 A2 (1982-01-01), None
patent: 0433 825 A1 (1991-06-01), None
patent: 6-188409 (1994-07-01), None
International Publication WO 93/05535 (Pike et al.), dated Mar. 18, 1993.
Noriyuki Iwamuro et al.: “1200 V MCCT: A New Concept Three Terminal MOS-Gated Thyristor”, ISPSD 97, 1997, pp. 245-246.
Greenberg Laurence A.
Infineon - Technologies AG
Jackson, Jr. Jerome
Lerner Herbert L.
Stemer Werner H.
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