Active solid-state devices (e.g. – transistors – solid-state diode – Regenerative type switching device – Lateral structure
Reexamination Certificate
2002-01-28
2003-12-02
Wille, Douglas A. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Regenerative type switching device
Lateral structure
C257S163000
Reexamination Certificate
active
06657240
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to a negative resistance diode device for high frequency RF applications, and more particularly, to a gate-controlled, negative resistance diode device that utilizes band-to-band tunneling.
(2) Description of the Prior Art
As CMOS technology continues to reduce in device scale, the operating frequency of these circuits increases. For example, the digital signals in state-of-the art microprocessors are operating in excess of about 500 MHz clock frequency and will approach about 1 GHz very soon. Further, the small signal operating frequency of CMOS transistors, fabricated at feature sizes of about 0.25 microns, is in the range of about 1 GHz for radio frequency (RF) wireless applications.
Typical on-chip clock generator circuits are presently based on ring oscillator designs wherein a series of inverters are connected in a ring. The operating frequency of such ring oscillators is determined by the total propagation delay from the first inverter to the last inverter. Often, these ring oscillator circuits consume a large chip area because many inverters must be placed in series. In addition, a large switching noise is generated by these ring oscillator designs.
As an alternative to CMOS inverters, devices that are called “negative resistance” diodes are known in the art. For example, impact ionization avalanche transit time (IMPATT) diodes and barrier injection transit time (BARITT) diodes may be used to create negative resistance diode functions. IMPATT and BARITT diodes have been found to be useful in the formation of oscillators and amplifiers for high frequency RF and microwave applications. However, as will be shown in the following observations, these prior art devices have several disadvantages.
Referring now to
FIG. 1
, a simplified diagram of an IMPATT diode device is shown. Further, a graph of the electric field distribution across this IMPATT device during normal operation is illustrated. The IMPATT device comprises semiconductor bulk regions
14
,
18
,
22
, and
26
. This semiconductor bulk region further comprises a source region
14
, a barrier region
18
, a drift region
22
, and a collector region
26
. A typical dopant profile is shown in the illustration. The source region
14
is heavily doped n-type (n+). The barrier junction
18
is doped p-type (p). The drift region
22
is very lightly doped, or nearly intrinsic, and may be either n-type (&igr;) or p-type (&ngr;). The collector region
26
is heavily doped p-type (p+).
The operating principle of the IMPATT diode is based on two effects: the generation of charge carriers via impact ionization and the finite transit time of such charge carriers in a depleted drift region. The IMPATT diode requires a dc bias voltage V
DC
30
. The dc bias voltage V
DC
30
creates a reverse bias across the source-to-barrier (n+/p) junction
14
and
18
. This dc bias voltage V
DC
30
is preferably high enough to deplete the drift region
22
and to be near the onset of reverse avalanche current. An ac voltage signal V
AC
34
is placed across the IMPATT diode device in series with the dc bias voltage V
DC
30
. As can be seen from the graph, the static electric field caused by the dc bias voltage V
DC
30
is spread across the barrier junction
18
and the drift region
22
.
Referring now to
FIG. 2
, the high frequency operation of the IMPATT device is shown. The ac voltage signal V
AC
34
is plotted
60
as a frequency multiple of time (&ohgr;t). During a positive cycle, between 0 and &pgr;, the magnitude of the ac voltage signal V
AC
34
is large enough to trigger significant impact ionization occurs at the source-to-barrier interface
14
and
18
. Electron-hole pairs are thereby generated and, later, multiplied by the avalanche mechanism. Holes are collected toward the barrier region (p) side
18
while the electrons are collected in the source region (n+) side
14
.
Due to the nature of avalanche multiplication, the maximum magnitude of the hole current, I
o
(t)
64
, occurs at the end of the positive cycle of the ac voltage signal V
AC
34
, or at the time &pgr;. Therefore, the maximum hole current I
o
(t)
64
generated in the source-to-barrier interface
14
and
18
exhibits a &pgr;/2 delay from the maximum ac voltage, which is typically known as the “&pgr;/2 avalanche delay.”
Once the holes enter the drift region
22
, the carrier transport mechanism comprises carrier drift because the drift region
22
is nearly intrinsic and is depleted. The external current flow I
e
(t)
68
begins just as the ac voltage signal V
AC
enters the negative cycle between &pgr; and 2&pgr;. If the drift region
22
is long enough such that the transit time or drift time is exactly &pgr; (wherein &pgr;=&ohgr;L/v
s
), then the external current I
e
(t) is 180 degrees out of phase with the ac voltage signal. In other words, a small-signal “negative resistance” has been achieved. This negative resistance actually delivers power to the external circuit from the diode device. Such a device may be used for the creation of an oscillator circuit, for example.
Referring now to
FIG. 3
, a BARITT diode device is illustrated in simplified form. An electric field distribution plot is given. A semiconductor bulk layer comprises a source region
108
, a graded barrier region
112
and
116
, a drift region
120
, and a collector
124
. The source junction
108
is heavily doped p-type (p+). The graded barrier region
112
and
116
comprises a moderately doped n-type region (n
1
)
112
and a heavily doped n-type region (n+)
116
. The drift region
120
comprises a lightly doped, or nearly intrinsic, region of semiconductor that is lightly doped n-type (n
2
). The collector region
124
is heavily doped p-type (p+).
The operating principle of the BARITT diode is based on two effects: the generation of charge carriers via barrier injection of a forward biased p-n diode and the finite transit time of such charge carriers in a depleted drift region. The BARITT diode requires a dc bias voltage V
DC
128
. The dc bias voltage V
DC
128
creates a forward bias of, for example, about 0.7 V across the source-to-barrier (p+
1
) junction
108
and
116
. This dc bias voltage V
DC
30
is preferably high enough to deplete the drift region
120
. An ac voltage signal V
AC
132
is placed across the BARITT diode device in series with the dc bias voltage V
DC
128
. The static electric field caused by the dc bias voltage V
DC
128
causes the drift region (n
2
)
120
to be fully depleted. The electric field is distributed
130
across the BARITT device as shown.
Referring now to
FIG. 4
, the high frequency operation of the IMPATT device is shown. The ac voltage signal V
AC
132
is plotted
150
as a frequency multiple of time (&ohgr;t). During a positive cycle, between 0 and &pgr;, the p+
1
is forward biased. Significant hole current, I
o
(t)
160
, is injected into the n
1
region
112
. Note that, the much lower doping of the n
1
region
112
compared to the p+ junction
116
means that the corresponding electron injection current from the n
1
region
112
to the p+ region
108
is negligible when compared to the magnitude of the hole current I
o
(t)
160
. Holes are collected toward the heavily doped portion of the barrier junction (n+)
116
.
Due to the nature of a forward biased p-n junction, the maximum magnitude of the hole current, I
o
(t)
160
, occurs at the midpoint of the positive cycle of the ac voltage signal V
AC
132
, or at the time &pgr;/2. Therefore, the maximum hole current I
o
(t)
160
generated exhibits no &pgr;/2 delay from the maximum ac voltage and is therefore “in phase” with the ac voltage.
Once the holes enter the drift region (n
2
)
120
, the carrier transport mechanism comprises carrier drift because the drift region
120
is nearly intrinsic and is depleted. The external current flow I
e
(t)
164
begins just as the ac voltage signal V
AC
132
hits midpoint of the positive
Ackerman Stephen B.
Pike Rosemary L. S.
Saile George O.
Taiwan Semiconductoring Manufacturing Company
Wille Douglas A.
LandOfFree
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