Gate controlled avalanche bipolar transistor

Details Gate controlled avalanche bipolar transistor Gate controlled avalanche bipolar transistor

1992-09-29

1994-09-06

Larkins, William D.

Active solid-state devices (e.g., transistors, solid-state diode

Bipolar transistor structure

Avalanche transistor

257367, H01L 2974, H01L 29784, H01L 2990

Patent

active

053451031

ABSTRACT:
An insulated gate controlled avalanche bipolar transistor has a heavily doped (with doping of at least 1.times.10.sup.18 cm.sup.-3) substrate and a lightly doped channel layer of the same conductivity type on the substrate. The source/emitter and drain/collector regions extend through the lightly doped surface layer to reach the heavily doped substrate, so that the junction between the drain and the heavily doped substrate promotes avalanche breakdown. A lightly doped region of the same type as the substrate is provided betwen the heavily doped substrate and the contact to the substrate, to provide a resistance between the substrate, which acts as the base of the transistor, and the substrate contact, to permit biasing of the base by resistive voltage drop across the resistance, while the lightly doped channel layer permits a low FET threshold voltage. The lightly doped resistance region may be located on the bottom of the substrate or on the top surface laterally spaced from the source/emitter and drain/collector regions.

REFERENCES:
patent: 4131908 (1978-12-01), Daub et al.
patent: 4242691 (1980-12-01), Kotani et al.
patent: 4697198 (1987-09-01), Komari et al.
patent: 4868621 (1989-09-01), Miyamoto

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