Gate control circuit for voltage drive switching element

Miscellaneous active electrical nonlinear devices – circuits – and – Gating – Accelerating switching

Reexamination Certificate

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Details

C327S434000, C326S017000

Reexamination Certificate

active

06285235

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a gate control circuit for turning on and off a voltage drive switching element such as an insulated gate semiconductor device of a MOS gate structure, for example, a MOS-FET, an IGBT (Insulated Gate Bipolar Transistor) and an IEGT (Injection Enhanced Gate Transistor).
2. Description of the Background
The insulated gate semiconductor device is used as a switching element of a power converter, for example an inverter which drives an induction motor, a frequency modulator and an uninterruptable power supply for supplying power to peripherals in case of a power failure.
Above all, the IGBT has been widely used in industrial equipment due to its voltage actuation characteristic and its capability of switching a relatively high current.
FIG. 1
shows a conventional gate control circuit for IGBT
1
. In
FIG. 1
, IGBT
1
is an insulated gate semiconductor device having a collector terminal C, an emitter terminal E and a gate terminal G. A gate control circuit
100
, shown by the chained line, is connected between the terminals G and E.
The gate control circuit
100
is composed of a first DC (Direct Current) power source
2
A, a second DC power source
2
B, a first switch
3
A for applying a positive voltage to IGBT
1
, a second switch
3
B for applying a negative voltage to IGBT
1
, and a gate resistor
4
. A series circuit of the gate resistor
4
, the first switch
3
A and the first DC power source
2
A is connected between the terminals G and E of IGBT
1
. Further, a series circuit of the second DC power source
2
B and the second switch
3
B is connected between the junction of the terminal E and a negative terminal of the first DC power source
2
A and the junction of the first switch
3
A and the gate resistor
4
. Furthermore, the terminal C and the terminal E are connected to a main circuit of a power converter (not shown).
IGBT
1
is turned on by applying a positive voltage across the terminals G and E, and is turned off by applying a negative voltage across the terminals G and E.
FIG. 2
is a timing chart showing a relationship between the voltage Vce and current Ic between a collector terminal C and an emitter terminal E of IGBT
1
, and the voltage Vge and current Ig between a gate terminal G and an emitter terminal E of IGBT
1
at the time IGBT
1
turns off.
Upon turn off, the second switch
3
B switches on in order to apply the negative voltage which is a driving voltage Vg. Then, the voltage Vge, called a mirror voltage, between the terminals G and E is maintained during turn off transition. The gate current Ig is almost constant during the transition. When the integration of the gate current Ig (electrical charge) reaches a certain amount of electrical charge, a current Ic flowing in IGBT
1
decreases and finally IGBT
1
turns off.
However, as shown in
FIG. 2
, there is a time delay to turn off IGBT
1
completely after switching on the second switch
3
B because the mirror voltage has a positive value for a while (a mirror time). The mirror voltage, between the terminals G and E, caused by a mirror effect being proper to IGBT
1
remains until electrical charge stored in stray capacitance between the terminals G and E is completely discharged. This delay time has an adverse influence on efficiency.
One method to reduce the delay time is to lower the resistance of the gate resistor
4
and increase the gate current Ig. But this approach gives rise to a surge voltage between the terminals G and E, because the gate current Ig rises suddenly. Therefore, lowering the resistance of the gate resistor
4
results in increasing a switching loss of the IGBT
1
. As a result, the resistance of the gate resistor
4
can not be changed easily.
Moreover, if a power converter is composed of a plurality of insulated gate semiconductor devices such as IGBT
1
respectively connected in serial or in parallel and the turn off delay times are different from each other, the power converter loses balance in the voltage or current applied to the insulated gate semiconductor devices. As a result, a high voltage or current is concentrated on one of the insulated gate semiconductor devices.
SUMMARY OF THE INVENTION
Accordingly, one object of this invention is to provide a gate control circuit which can reduce a delay time to turn off an insulated gate semiconductor device after switching off a switch without lowering the resistance of the gate resistor.
Another object of this invention is to provide a gate control circuit which can stop an outbreak of a surge voltage applied to an insulated gate semiconductor device.
Another object of this invention is to provide a power converter circuit which can simultaneously turn on or turn off a plurality of insulated gate semiconductor devices.
These and other objects are achieved by providing a new and improved gate control circuit for turning on and off an insulated gate semiconductor device having gate, emitter and collector terminals; including a first DC power source coupled to the gate terminal via a first switch and configured to apply a positive voltage to the gate terminal in order to turn on the insulated gate semiconductor device when the first switch is turned on and the second switch is turned off; a second DC power source coupled to the gate terminal via a second switch and configured to apply a negative voltage to the gate terminal in order to turn off the insulated gate semiconductor device when the second switch is turned on and the first switch is turned off; a parallel circuit of a diode and a capacitor coupled in series to the second switch; and a turn off assist circuit configured to produce a negative charge on the capacitor to assist in turning off the insulated gate semiconductor device.
According to one aspect of this invention, there is provided a power converter circuit having a plurality of insulated gate semiconductor devices, each provided with a respective gate control circuit, wherein equalization of delay times for turning off the insulated gate semiconductor devices is achieved by controlling a charge stored in the capacitor of each gate control circuit based on detected collector-emitter voltages or detected emitter currents.


REFERENCES:
patent: 4885486 (1989-12-01), Shekhawat et al.
patent: 5055721 (1991-10-01), Majumdar et al.
patent: 5500619 (1996-03-01), Miyasaka
patent: 5808504 (1998-09-01), Chikai et al.
patent: 5986484 (1999-11-01), Kimata
patent: 7-67317 (1995-03-01), None
patent: 7-264028 (1995-10-01), None

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