Gate compensation delay and delay lines

Details Gate compensation delay and delay lines Gate compensation delay and delay lines

1993-03-31

1995-11-07

Sikes, William L.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Having specific delay in producing output waveform

327278, 327263, H03H 1126

Patent

active

054650658

ABSTRACT:
An apparatus for and method of producing a highly accurate and easily recalibratable delay line using only digital components. A serial string of digital gates or buffers is coupled together to permit an input signal to cascade through all of the gates or buffers. The length of time for the signal to cascade is determined by the average propagation delay of the buffers and the number of buffers in the serial string. Taps at the outputs of the buffers permit selection of the desired delay by selecting the output from less than all of the buffers in the string. Calibration is accomplished by passing a calibration pulse of predetermined pulse width through the delay string of buffers. A calibration register records the buffer position of the leading edge of the calibration pulse at the time the trailing edge of the calibration pulse enters the string. The number of buffers thus identified provides a delay equal to the length of the calibration pulse under the current ambient conditions. The delay line is periodically recalibrated to compensate for changes in ambient conditions.

REFERENCES:
patent: 5245231 (1993-09-01), Kocis
patent: 5349612 (1994-09-01), Guo

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