Gate circuit having increased voltage handling capability

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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307576, 307594, 307597, 307603, 307605, 307451, 307279, H03K 17687, H03K 513, H03K 19094, H03K 326

Patent

active

051824795

ABSTRACT:
A gate circuit includes an N-channel and a P-channel insulated gate field-effect transistor whose parallel-connected drain-source paths constitute an analog signal gate and a control circuit, connected to the respective gate electrodes, to turn on and/or turn off the two field-effect transistors. In order to handle signals whose voltage value is higher than the maximum permissible drain-source voltage in the on-state of the N-channel field-effect transistor, means are provided, for turning on the N-channel field-effect transistor at least at a drain-source voltage below a predetermined value. In an embodiment of the invention the means include delay means coupled to the control circuit for turning on the N-channel field-effect transistor with a delay relative to the P-channel field-effect transistor. In another embodiment of the invention the means include switching means arranged in series with the analog signal gate, for temporarily connecting the signal gate to at least one auxiliary voltage.

REFERENCES:
patent: 4001606 (1977-01-01), Dingwall
patent: 4518873 (1985-05-01), Suzuki et al.
patent: 4695744 (1987-09-01), Giordano
patent: 4707620 (1987-11-01), Sullivan et al.
patent: 4797579 (1989-01-01), Lewis
patent: 4801819 (1989-01-01), Theus et al.
patent: 4829199 (1989-05-01), Prater
patent: 4874971 (1989-10-01), Fletcher
"Device Parameter Independent Delay Circuit", IBM Technical Disclosure Bulletin, vol. 31, No. 1, Jun. 1988, pp. 21-23.

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