Gate circuit for insulated gate semiconductor device

Details Gate circuit for insulated gate semiconductor device Gate circuit for insulated gate semiconductor device

2000-02-25

2001-12-25

Lam, Tuan T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Gating

Utilizing three or more electrode solid-state device

C327S389000, C327S430000

Reexamination Certificate

active

06333665

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to gate circuits for insulated gate semiconductor devices.
2. Description of the Related Art
Insulated gate semiconductor devices having a MOS type gate structure, for example MOS-FET, IGBT (Insulated Gate Bipolar Transistor) and IEGT (Injection Enhanced Gate Transistor), are voltage-driven types. Charging and discharging currents for the electric charge of the gate capacitance flow momentarily during ON/OFF switching but no gate current flows when in a steady state. Consequently, the gate power may be made extremely small, and also the high-speed operation that is a characteristic of the MOS composition is possible. Therefore, the development of this type of voltage-driven semiconductor device has been promoted in recent years, and they are beginning to be applied to power converters through the development of high voltage, large current (for example, 4.5 kV-1000 A type) insulated gate semiconductor devices.
As insulated gate semiconductor devices are being made higher voltage and larger current, so the respective capacitances between the collector and emitter, between the collector and the gate, and between the gate and the emitter are becoming larger.
FIG. 1
is a simplified drawing showing a prior art gate circuit that drives an insulated gate semiconductor device. Control electrode (gate) G of insulated gate semiconductor device
10
is supplied with ON/OFF control signals by semiconductor switches
12
and
13
via gate resistor
11
.
FIG. 2
is a circuit for a single-phase part, for example the U-phase part, when an inverter circuit has been composed using insulated gate semiconductor devices.
FIG. 3
shows the gate voltage waveforms and the insulated gate semi-conductor device voltage (Vce) and current (Ic) when a PWM inverter is operated by the gate driving circuit shown in FIG.
1
. At turn-ON and turn-OFF times, a Miller voltage period appears due to the capacitance characteristic between the gate and the emitter. In particular, at turn-ON times, there is a tendency for the Miller voltage period to become longer, the higher the withstand-voltage of the device. This reason is because, in particular, the capacitance between gate and emitter exists in the voltage between the collector and the emitter, and when voltage between collector and emitter reduces due to turn-ON, the capacitance between gate and emitter increases.
Here, the Miller voltage means a gate voltage that may turn ON insulated gate semiconductor device
10
from the OFF state, in other words a threshold voltage. Consequently, the Miller voltage period means an interim period in which the Miller voltage is generated.
In a PWM inverter, because the load current is made more sine-wave, it is desirable to make its switching frequency high. However, since there are restrictions on the minimum ON and dead time due to the above Miller period, the upper limit frequency becomes restricted. The gate resistor may be made smaller in order to shorten the Miller period. However, the insulated gate semiconductor device switching characteristic also becomes faster, and there are cases when damage is caused to the device due to the sharp current rise (di/dt) at turn-ON and the sharp voltage rise (dv/dt) at turn-OFF.
As shown in
FIG. 3
, at turn-ON and turn-OFF, the gate signals for the upper and lower arms (U and V) provide dead period To and prevent upper/lower shorting. However, when the insulated gate semiconductor device of the opposite arm turns ON, due to the division of the capacitance between the various terminals, in particular, a phenomenon is observed (Section A of
FIG. 3
) of the gate-to-emitter voltage rising in the positive direction due to the sharp variation of current (di/dt) and the sharp variation of voltage (dv/dt). The provision of a capacitor between the gate and the emitter is effective in preventing this. However, when a capacitor is provided, the problem arises that switching losses increase due to the switching time of the insulated gate semiconductor device becoming slower.
It is desirable to solve the problem of
(1) the phenomenon of the gate-to-emitter voltage being raised in the positive direction by the dv/dt due to the turn-ON of a pair of arms with a high-voltage, large-current insulated gate semiconductor device without providing a capacitor between the gate and the emitter, and
(2) having to shorten the dead time of a PWM inverter due to shortening the Miller period of that insulated gate semiconductor device.
SUMMARY OF THE INVENTION
Accordingly one object of the present invention is to provide a novel and highly reliable gate driving method that may improve the high-frequency operation of an insulated gate semiconductor device and stably drive power conversion equipment such as inverters.
In order to achieve the above object, the present invention is composed in such a way that:
multiple semiconductor device groups are provided, in which P-channel semiconductor devices and N-channel semiconductor devices are connected in series (totem pole connection);
the anode terminals of each group are connected to a positive control power source;
the connection point of the first semiconductor device group is connected to the gate of an insulated gate semiconductor device via a resistor;
the connection point of the second semiconductor device group is connected to the gate of the insulated gate semiconductor device without passing through a gate resistor; and
the signals to the respective control electrodes of the second semiconductor device group are supplied via delay circuits that delay the ON/OFF signals from a switching signal source by specified time delays.
Moreover, the present invention is composed in such a way that:
in the case of the connection point potential of the first semiconductor device group being positive, the control signal is supplied to the control electrode of the positive side semiconductor device of the second semiconductor device group after being delayed for a specified time, and
in the case of the said potential being negative, the control signal is supplied to negative side semiconductor device of the said second group after being delayed for a specified time.


REFERENCES:
patent: 5852538 (1998-12-01), Masui
patent: 5929665 (1999-07-01), Ichikawa et al.
patent: 5963071 (1999-10-01), Dowlatabadi
patent: 6133757 (2000-10-01), Huang et al.
patent: 8-018423 (1996-01-01), None

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