Gate circuit

Details Gate circuit Gate circuit

1999-08-05

2001-08-07

Cunningham, Terry D. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Gating

Accelerating switching

C327S440000, C327S432000, C327S478000

Reexamination Certificate

active

06271708

ABSTRACT:

BACKGROUND OF INVENTION
1. Field of Invention
The present invention relates to the gate circuits of MOS gate type semiconductor elements.
2. Description of the Related Art
MOS gate type semiconductor elements have many advantages, such as small gate circuits and low energy consumption compared with thyristor semiconductor elements.
FIG. 1
is a block diagram of a single-phase inverter that uses MOS gate type semiconductor elements.
In
FIG. 1
, S
1
~S
4
are MOS gate type semiconductor elements,
3
is a capacitor and
4
is the load. Here, a plurality of IEGT are used as the MOS gate type semiconductor elements.
Gate circuits G
1
~G
4
are connected to MOS gate type semiconductor elements S
1
~S
4
. The detail of this is shown in FIG.
2
.
The gate circuit has ON gate power source E
on
, OFF gate power source E
off
, turn-on switch SW
on
, and turn-off switch SW
off
. The node between turn-on switch SW
on
and turn-off switch SW
off
is connected to gate G of the MOS gate type semi-conductor element via gate resistor R
g
. The node between ON gate power source E
on
and OFF gate power source E
off
is connected to emitter E of the MOS gate type semiconductor element.
Normally, about 15V is used for ON gate power source E
on
and OFF gate power source E
off
, and about 10□for gate resister R
g
.
The relationship between MOS gate type semiconductor elements S
1
and S
2
or between MOS gate type semiconductor elements S
3
and S
4
is referred to as that of upper and lower arms in a single-phase inverter. Normally, upper and lower arms, for example MOS gate type semiconductor elements S
1
and S
2
, do not switch simultaneously. One or other puts the gate circuit in a negative bias state so that there is no fire (turn-on), and the other is switched ON/OFF.
However, there are the following problems with prior art gate circuits.
Provided the gate potential of the element, for example element S
1
, that is negatively biased is sufficiently negatively biased, there is no problem. However, when the other element, S
2
, turns ON, if the gate potential of element S
1
, that is to say the negative bias potential, is transiently overcome by the positive side as shown in
FIG. 3
, element S
1
will also turn ON. Thus, the arm is shorted out by elements S
1
and S
2
turning ON simultaneously.
This phenomenon of the transient overcoming of the negative bias is becoming a problem as MOS gate type semiconductor elements are being made to withstand higher voltages.
Another problem occurs when attempting to turn OFF multiple parallel-connected elements with one gate circuit. That is to say, the gate potentials of the elements become unstable and current unbalance arises through the generation of circulating currents between the gate circuit emitter wiring and the principal circuit emitter wiring.
This phenomenon is explained using FIG.
4
and FIG.
5
.
FIG. 4
is a block diagram of a single-phase inverter in which each arm is composed of two parallel-connected elements.
FIG. 5
is an expanded detail drawing of part of FIG.
4
.
Here, elements S
11
and S
12
are in the conductive state and a current is flowing; then elements S
11
and S
12
are turned off to break the current. When this is done, currents i
11
and i
12
generate the circulating current of loop A. The potentials of the emitter elements for the gates of elements S
11
and S
12
oscillate due to variation of this current and the wiring impedance, and current-unbalance occurs.
SUMMARY OF THE INVENTION
Accordingly, one object of the present invention is to provide a novel gate circuit in which the negative bias does not fluctuate when switching, and circulating currents between the gate circuit and the parallel connected gates are eliminated.
To achieve the above object, in a gate circuit having a turn-off gate circuit composed of:
an OFF gate power source of which one terminal that becomes the power source when a semiconductor switching element turns off is connected to the emitter of the semiconductor switching element, and
a first switch that connects the other terminal of the above OFF gate power source and the gate of the semiconductor switching element via a resistor,
with the gate circuit concerned in the present invention, a second switch is provided that connects the other terminal of the above OFF gate power source and the gate of the semiconductor switching element. By closing the second switch at a specified timing, it becomes connected to the OFF gate power source with passing via a resistor, and the effect of the negative bias is made much more stable. Therefore, erroneous fire (ignition) is eliminated.
And moreover, in a gate circuit having a turn-off gate circuit composed of:
A first OFF gate power source of which one terminal that becomes the power source when a semiconductor switching element turns off is connected to the emitter of the semiconductor switching element, and
a first switch that connects the other terminal of the above first OFF gate power source and the gate of the semiconductor switching element via a resistor,
with the gate circuit concerned in the present invention:
a second OFF gate power source, of which one terminal that has a greater absolute value than the above first OFF gate power source is connected to the emitter of the semiconductor switching element and
a second switch that connects the other terminal of the above second OFF gate power source and the gate of the semiconductor switching element
are provided. By closing the second switch at a specified timing, it becomes connected to the second OFF gate power source that has a greater absolute value than the first OFF gate power source, and the effect of the negative bias is made much more stable. Therefore, erroneous fire is eliminated.
With the gate circuit concerned in the present invention, the above second switch is connected to the gate of the above semiconductor switching element via a second resistor that is smaller than the above resistor. By closing the second switch at a specified timing, it becomes connected to the OFF gate power source via the resistor that is smaller than the above resistor, and the effect of the negative bias is made much more stable. Therefore, erroneous fire is eliminated.
And moreover, with the gate circuit concerned in claim
4
of the present invention, the above second switch is closed at a specified time interval after the above switch has been closed. By closing the second switch after the elapsing of the approximate time for completion of the turn-off operation, a greater negative bias can be applied than in prior art. Therefore, erroneous fire is eliminated.
And moreover, with the gate circuit concerned in the present invention, the said second switch is closed if the gate voltage falls to a specified voltage or below. By closing the second switch when the gate voltage falls to approximately the voltage at which the essential part of the turn-off operation is completed, a greater negative bias can be applied than in prior art. Therefore, erroneous fire is eliminated.
And moreover, with the gate circuit concerned in the present invention, the above second switch is closed when the current flowing in the above semiconductor switching element falls to a set current value or below. By closing the second switch when the current flowing in semiconductor switching element falls to approximately the voltage at which the essential part of the turn-off operation is completed, a greater negative bias can be applied than in prior art. Therefore, erroneous fire is eliminated.
And moreover, with the gate circuit concerned in the present invention, the above second switch is closed when the voltage across the above semiconductor switching element becomes a set voltage value or above. By closing the second switch when the voltage across the semiconductor switching element rises to approximately the voltage at which the essential part of the turn-off operation is completed, a greater negative bias can be applied than in prior art. Therefore, erroneous fire is eliminated.
And moreover, with the gate cir

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