Gate bootstrapped CMOS sample-and-hold circuit

Details Gate bootstrapped CMOS sample-and-hold circuit Gate bootstrapped CMOS sample-and-hold circuit

2001-09-06

2003-02-25

Nuton, My-Trang (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By amplitude

C327S589000

Reexamination Certificate

active

06525574

ABSTRACT:

FIELD OF THE INVENTION
This invention relates generally to electronic circuits and more specifically to a low distortion and high speed, sample and hold circuit.
BACKGROUND OF THE INVENTION
A sample and hold circuit is a circuit that monitors a signal provides its value at predetermined times, and keeping it constant thereafter.
A sample and hold circuit with boosted clock is shown in FIG.
1
. This sample and hold circuit includes a switch
100
coupled to a load capacitor
110
. The load capacitor
110
holds the input voltage V
IN
at predetermined times which are controlled by the switch
100
. The control of switch
100
is determined by the voltage on the gate of switch
100
.
To have the highest transfer of voltage from V
IN
to the load capacitor
110
, an n type switch
100
is employed. However because an n type switch is chosen, the substrate is connected to ground when a p-well is not available which causes distortion in the sampled signal.
In
FIG. 2
a,
a replica circuit
130
shown as a NFET acting as a diode is added in the current path with a current source outputting the current I
BIAS
. This generates a voltage V
GS2
to be placed on the boost capacitor
120
. The voltage generated by diode
130
will follow the threshold voltage variations of switch
100
, as a result of the fact that diode
130
is a replica of switch
100
. As a consequence of the circuit of
FIG. 1
, the voltage applied to switch
100
will have an additional or boost charge applied to the gate of switch
100
as a result of the voltage across diode
130
. Switch
140
and switch
150
both lead to problems during the operation of these switches. If for example, a PMOS switch is used in an n well process, the well of the transistor has to be connected to a voltage higher than a maximum voltage applied to the gate of switch
100
. Alternatively, if NMOS switches are used for switches
140
and
150
then the clock signal to control switch
140
and switch
150
has to be boosted. Boosting the clock signal results in an increased amount of circuitry and complexity and consequently is costly in both chip area and production costs. Additionally, the switch
150
is used to turn off switch
100
by connecting the gate of transistor
100
to ground. All these problems create additional constraints on the trade off of speed, precision, and power consumption of the design for the sample and hold circuit. The voltage on switch
140
is equal to voltage V
BIAS
+V
GS2
and this causes problems for switch
140
in that once the voltage on the drain of goes above VDD, the switch
140
could close without the clock signal CK
2
being applied. This is undesirable.
An additional problem is the size of switch
100
. Switch
100
may be implemented by an NFET and at a certain speed, the switch
100
represents a specific on resistance value. With higher speeds, the on resistance value of switch
100
should be lowered. To lower the on resistance, a higher physical size of switch
100
is required. However, increasing the size of switch
100
leads to an increased parasitic capacitance which results from a wider channel. However, this higher capacitance to parasitic slows the response in terms of frequency.
Consequently, it is required to overcome the problem of using the PMOS switch with the n-well process without using the boosted clock signals and overcome the problem of a high-speed operation.
SUMMARY OF THE INVENTION
The present invention provides an increased voltage to the gate of the switch to avoid increasing the size of the switch and effectively lowering the on resistance of the switch. Thus, the speed of the switch and ultimately the speed of the sample and hold circuit is increased.
Advantageously, this higher voltage does not affect the switches controlling the gate of the switch. To control the gate of the switch a boost voltage is applied and this boost voltage does not adversely affect the operations of switches used to produce the boost voltage.


REFERENCES:
patent: 5084634 (1992-01-01), Gorecki
patent: 5945872 (1999-08-01), Robertson et al.
patent: 6052000 (2000-04-01), Nagaraj
patent: 6060914 (2000-05-01), Nunokawa
patent: 6215348 (2001-04-01), Steensgaard-Madsen
patent: 6310565 (2001-10-01), Ong et al.
patent: 6323697 (2001-11-01), Pavan

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