Gate array with reduced isolation

Details Gate array with reduced isolation Gate array with reduced isolation

1985-05-17

1986-07-22

Wojciechowicz, Edward J.

357 41, 357 45, 357 46, 357 48, 357 68, H01L 2978

Patent

active

046022708

ABSTRACT:
An improved gate array employs long strips of gates instead of current blocks. Isolation of selected adjacent circuits is provided by connecting positions of the area between transistor gates to VCC or ground. Room for passage of connecting lines across a column is provided by shifting the positions of circuits along a column to open a sufficient quantity of unused gates.

REFERENCES:
patent: 4161662 (1979-07-01), Malcolm et al.

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