Gate array system in which functional blocks are connected by fi

Active solid-state devices (e.g. – transistors – solid-state diode – Gate arrays – With particular chip input/output means

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Details

257207, 257210, H01L 27118

Patent

active

059172061

ABSTRACT:
An gate array system characterized in including, on a semiconductor chip, an internal cell region where internal cells are arranged in lattice and a cell region for input/output circuit including an array of input/output circuit cells disposed on the circumference of the internal cell region, and characterized in that a positional relationship between an internal cell at a specific position of the internal cell region and a specific input/output cell constituting the cell region for input/output circuit or a functional block formed at a specific position of the cell region for input/output circuit is constant irrespective of the size of a semiconductor chip.

REFERENCES:
patent: 5060046 (1991-10-01), Shintani

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