Gate array semiconductor integrated circuit device

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357 45, 357 41, 364491, H01L 2702

Patent

active

051191580

ABSTRACT:
A set of input and output buffers are arranged in an outer peripheral portion of a semiconductor chip and a macro region and a set of internal gates are arranged in an inside portion of the semiconductor chip. The input and output buffers are connected to the internal gates through a boarder region between the macro and the set of the internal gates.

REFERENCES:
patent: 4688070 (1987-08-01), Shiotari et al.
patent: 4833620 (1989-05-01), Takahashi
patent: 4839820 (1989-06-01), Kinoshita et al.
patent: 4887135 (1989-12-01), Cheney et al.
patent: 4959704 (1990-09-01), Isomura et al.

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