Gate array semiconductor device

Details Gate array semiconductor device Gate array semiconductor device

1998-07-30

2000-07-04

Munson, Gene M.

Active solid-state devices (e.g., transistors, solid-state diode

Gate arrays

Having specific type of active device

257206, 257351, H01L 2710

Patent

active

060842555

ABSTRACT:
In each of basic cells (BC) arranged in array in an SOI layer, PMOS and NMOS transistors are symmetrically formed. Body regions (11) and (12) are formed to divide source/drain layers (1) and (2), respectively, and gate electrodes (3) and (4) are formed on the body regions (11) and (12) respectively to sandwich gate insulating films therebetween. The gate electrodes (3) and (4) are connected at their both ends to gate contact regions (5) to (8), respectively, and the body regions (11) and (12) are connected at their one ends to body contact regions (9) and (10), respectively. The body contact regions (9) and (10) are so arranged as to sandwich the gate contact regions (5) and (7) together with the gate electrodes (3) and (4), respectively. Being of a SOI type, the device achieves high-speed operation and low power consumption. Further, with positional relation between the body contact regions (9), (10) and the gate contact regions (5), (7), the device is capable of freely setting the transistors to be of either a gate control type or a gate fixed type. As a result, the gate array type semiconductor device achieves high-speed operation and low power consumption.

REFERENCES:
patent: 5001528 (1991-03-01), Bahraman
patent: 5633524 (1997-05-01), Ueda et al.
patent: 5793068 (1998-08-01), Mahant-Shetti
patent: 6008510 (1999-12-01), Kumagai
Takakuni Douseki, et al. "A 0.5V SIMOX-MTCMOS Circuit with 200ps Logic Gate", ISSCC96/Session 5/Technology Directions: High Speed, Low-Power/Paper TP 5.4, pp 84-85, and 423.
Tsuneaki Fuse, et al. "0.5V SOI CMOS Pass-Gate Logic", ISSCC96/Session 5/Technology Directions: High Speed, Low-Power/Paper TP 5.6, pp 88-89, and 424.
Tsuneaki Fuse, et al., "A 0.5V 200MHz 1-Stage 32b ALU Using a Body Bias Controlled SOI Pass-Gate Logic", 1997 IEEE International Solid-State Circuits Conference, SA 17.1 pp 286-287, and 472.

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