Gate array LSI device using PNP input transistors to increase th

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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307456, 307255, 307466, 364490, 365 72, H03K 19013, H03K 19088, H03K 19092, H03K 1704

Patent

active

046895027

ABSTRACT:
A gate array LSI device having inner gate circuits whose performance is not affected by the load condition and having a large fan-out number. The inner gate circuit comprises one or more PNP-type transistors, each of which receives an input signal at the base thereof, a first NPN-type transistor whose base is connected to the emitters of the PNP-type transistors, and an output buffer circuit. The output buffer circuit includes a second NPN-type transistor, which is controlled by the signal at the emitter of the first NPN-type transistor and outputs electric charges from an output terminal, and a third NPN-type transistor, which is controlled by the signal at the collector of the first NPN-type transistor and which is connected in series with the second NPN-type transistor so as to supply a charging current to the output terminal.

REFERENCES:
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patent: 3482111 (1969-12-01), Gunderson et al.
patent: 3643232 (1972-02-01), Kilby
patent: 3999080 (1976-12-01), Weathersby, Jr. et al.
patent: 4045689 (1977-08-01), Tietz
patent: 4131808 (1978-12-01), Kuo
patent: 4174541 (1979-11-01), Schmitz
patent: 4535258 (1985-08-01), Tanizawa

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