Gate array LSI

Details Gate array LSI Gate array LSI

1997-09-02

1999-11-02

Nguyen, Viet Q.

Static information storage and retrieval

Addressing

Plural blocks or banks

326 41, H01L 2710

Patent

active

059783010

ABSTRACT:
The present invention relates to the improvement in the degree of on-chip integration of memory cells utilizing a gate array layout. A plurality of three-transistor DRAM cells are disposed on a semiconductor chip implementing a regular cross-point array, each DRAM cell is made up of two nMOS transistors and one pMOS transistor formed in one basic cell. The semiconductor chip disposes therein nMOS memory-cell blocks and pMOS memory-cell blocks alternately, effectively utilizing the gate array layout.

REFERENCES:
patent: 5500609 (1996-03-01), Kean
patent: 5610533 (1997-03-01), Arimoto et al.
patent: 5654931 (1997-08-01), Tamba et al.
patent: 5787033 (1998-07-01), Maeno

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