Gate array layout for interconnect

Details Gate array layout for interconnect Gate array layout for interconnect

2001-06-22

2004-01-27

Lee, Eddie (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Gate arrays

Having specific type of active device

C257S208000

Reexamination Certificate

active

06683335

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a semiconductor integrated circuit, and in particular to an effective technique that is used for a gate array employed for high integration and low power.
BACKGROUND OF THE INVENTION
To appropriately support the production of a variety of small lots of ASIC (Application Specific Integrated Circuit) chips, elements such as transistors are manufactured in advance for use as base cells. Later, in addition to first layer lines provided for such cells, lines for a customized circuit, designed in accordance with customer specifications, are provided to produce ASICs that can perform functions required for particular applications. This production method thus provides means for flexibly coping with the needs of clients, and contributes to a reduction in the time required for the delivery of orders. In one type of ASIC, a gate array, p-type transistors and n-type transistors are arranged in separate arrays as basic cells. Then, when customized circuit lines for the transistors (basic cells) are added, a logic circuit that satisfies the needs of a customer can be provided. It should be noted that the transistors used for this purpose are MISFETs (Metal Insulator Semiconductor Field Effect Transistors).
FIG. 1
is a plan view of an example conventional gate array. An n well
2
and a p well
3
are formed on the main face of a semiconductor substrate
1
. Gate lines
4
are formed across the n well
2
and the p well
3
. Each of the gate lines
4
includes a gate electrode
4
a
, which functions as the gate of a MISFET, and a contact (connection region)
4
b
for the upper layer line. The contact
4
b
is formed on an element separation region
5
, and a contact member for effecting a connection with the first layer line is deposited thereon. Doped regions
6
, which are formed above the n well
2
on either side of gate electrodes
4
a
, are p-type regions, and function as the sources or the drains for p-type MISFETs. The doped regions
6
, which are formed above the p well
3
, are n-type regions and function as the sources or the drains of n-type MISFETs. A gate line
4
, an impurity region
6
and a channel region below a gate electrode
4
a
constitute one MISFET.
Multiple p-type MISFETs and multiple n-type MISFETs are arranged in like arrays along the respective well regions (the n well
2
and the p well
3
) in the x direction (first direction) in which the well regions are formed and extended. Adjacent MISFETs (p-type MISFETs or n-type MISFETs) share the impurity regions
6
that serve as the sources or drains. The arrays of p-type MISFETs and n-type MISFETs are located adjacent to each other in the y direction (second direction), and since the p-type and the n-type MISFETs are arranged adjacently, wiring of a CMOS circuit is facilitated.
To use this gate array to constitute an inverter, for example, only the following connections need be made.
FIG. 2A
is a plan view of an example inverter using the conventional gate array, and
FIG. 2B
is a circuit diagram for the inverter.
In
FIGS. 2A and 2B
, a MISFET (Qp
1
) that includes a gate line
4
-
1
p
and a MISFET (Qn
1
) that includes a gate line
4
-
1
n
are employed. In the following explanation, a p-type MISFET that includes a gate line
4
-kp is denoted by Qpk (k is a natural number), and an n-type MISFET that includes a gate line
4
-kn is denoted by Qnk. One of the impurity regions
6
(to the left of the gate line
4
-
1
p
) of the Qp
1
and a line LVdd are connected by a contact
7
, and one of the impurity regions
6
(to the left of the gate line
4
-
1
n
) of the Qn
1
and a line LVss are connected by a contact
7
. The other impurity region
6
(to the right of the gate line
4
-
1
p
) of the Qp
1
and the other impurity region
6
(to the right of the gate line
4
-
1
n
) of the Qn
1
are connected via a line L
1
and contacts
7
. The gate line
4
-
1
p
of the Qp
1
and the gate line
4
-
1
n
of the Qn
1
are connected via contacts
7
and a line L
2
formed on respective contacts
4
b
. The line L
2
corresponds to the input IN of the inverter, and the line L
1
corresponds to the output OUT of the inverter.
Further, to use the gate array to constitute a NAND circuit, for example, only the following connections need be made.
FIG. 3A
is a plan view of an example NAND circuit using the conventional gate array, and
FIG. 3B
is a circuit diagram showing the NAND circuit. It should be noted that the well regions are not shown in the plan views following
FIG. 3
for the simplification of the drawings.
The NAND circuit comprises an MISFET (Qp
2
) that includes a gate line
4
-
2
p
, an MISFET (Qp
3
) that includes a gate line
4
-
3
p
, an MISFET (Qn
2
) that includes a gate line
4
-
2
n
, and an MISFET (Qn
3
) that includes a gate line
4
-
3
n
. One impurity region
6
of the Qp
2
and one impurity region
6
of the Qp
3
are connected to a line LVdd via contacts
7
and one impurity region
6
of the Qn
3
is connected to a line LVss via a contact
7
. The impurity region
6
shared by the Qp
2
and the Qp
3
and the impurity region
6
of the Qn
2
are connected via a line L
3
and contacts
7
. The gate line
4
-
2
p
of the Qp
2
and the gate line
4
-
2
n
of the Qn
2
are connected via a line L
4
in the same manner as described above, and the gate line
4
-
3
p
of the Qp
3
and the gate line
4
-
3
n
of the Qn
3
are connected via a line L
5
. The line L
5
corresponds to the input IN
2
of the NAND circuit, the line L
4
corresponds to the input IN
3
of the NAND circuit, and the line L
3
corresponds to the output OUT of the NAND circuit.
The first layer lines (LVdd, LVss and L
1
to L
5
) are formed on an interlayer insulating film (not shown) that covers the gate lines, and generally are composed of a metal such as tungsten, or of polysilicon. The contacts
7
are conductive members provided inside connection holes that are formed in the interlayer insulating film. The contacts
7
are made of the same material as the first layer lines, or are separately provided as a plug from the first layer line.
When arbitrary lines are employed for the gate array as has previously been described, logic circuits can be produced. For an inverter or a NAND circuit, the gate lines of p-type MISFETs and n-type MISFETs can be interconnected by using the shortest possible lines (L
2
, L
4
and L
5
) to connect adjacent, vertically arranged (in the y direction) MISFETs.
However, for a latch circuit in
FIGS. 4A and 4B
, the gate lines of a diagonally arranged p-type and n-type MISFET must be connected.
FIG. 4A
is a plan view of a latch circuit using the conventional gate array, and
FIG. 4B
is a circuit diagram of the latch circuit.
When two MISFETs having the input IN
4
terminal of the latch circuit as a gate input terminal are defined as Qp
4
and Qn
4
, the gate line
4
-
4
p
of the Qp
4
and the gate line
4
-
4
n
of the Qn
4
are connected by the shortest line (line L
6
), as is shown in FIG.
4
B. Since it is rational that MISFETs adjacent to Qp
4
and Qn
4
should be selected as those connected in series to Qp
4
and Qn
4
, Qp
5
and Qn
5
are selected.
However, the gate line
4
-
5
p
of Qp
5
should not be connected to the gate line of Qn
5
, but must be connected to the gate line of another n-type MISFET (Qn
7
in FIG.
4
A). Further, the gate line
4
-
5
n
of Qn
5
must be connected to the gate line of a p-type MISFET (Qp
6
in
FIG. 4A
) other than Qp
5
. Therefore, as is shown in
FIG. 5
, when the gate line
4
-
5
n
and the gate line
4
-
6
p
are connected by using the line L
7
which travels the shortest distance, the gate lines
4
-
5
p
and
4
-
7
n
have to be connected by detouring around line L
8
. It should be noted that
FIG. 5
is a plan view of a portion extracted from FIG.
4
A.
When the lines intersect for the interconnection of the gate lines of a p-type MISFET and an n-type MISFET, as described above, a line for detouring around a line (first layer line) for connecting gate lines must be found, so that devices located in do

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