Gate array integrated circuit using Schottky-barrier FETs

Details Gate array integrated circuit using Schottky-barrier FETs Gate array integrated circuit using Schottky-barrier FETs

1984-11-26

1987-05-05

Larkins, William D.

357 41, 357 68, 357 71, H01L 2704

Patent

active

046636463

ABSTRACT:
A gate array integrated circuit in which gate cells are each composed of a DCFL circuit using Schottky-barrier FETs. A plurality of basic gate cells is arrayed in one direction to form a basic cell array, and such basic cell arrays are arranged parallel to each other. VDD lines and GND lines are provided to apply an operating voltage to the basic gate cells. In order to stably operate the gate array integrated circuit of DCFL structure in which the logical amplitude and noise margin are small, the VDD lines and the GND lines are arranged perpendicular to each other such that the number of the basic gate cells which are connected to each of the VDD lines is larger than that of the basic gate cells which are connected to each of the GND lines. According to this layout, the potential difference (voltage drop) developed in the GND lines by operation current is reduced.

REFERENCES:
patent: 3808475 (1974-04-01), Buelow et al.
Japanese Journal of Applied Physics, vol. 22, Supplement 22-1, p. 345, "500 Gates GaAs Gate Array"; N. Toyoda et al.; 1983.
Technical Digest, 1983 GaAs IC Symposium, p. 178, "A High Yield GaAs Gate Array Technology and Applications"; A. Rode et al.; Oct., 1983.
Technical Digest, 1983 Custom Integrated Circuits Conference, p. 32, "A 432-Cell GaAs SDFL Gate Array with On-Chip 64-Bit RAM"; T. Vu. P. Roberts et al.; May, 1983.

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