Gate array having transistor buried in interconnection region

Details Gate array having transistor buried in interconnection region Gate array having transistor buried in interconnection region

1988-02-09

1989-07-25

Larkins, William D.

357 45, H01L 2704

Patent

active

048518913

ABSTRACT:
A gate array comprises a semiconductor substrate, a plurality of mutually parallel basic cell columns each made up of a plurality of basic cells formed on the semiconductor substrate, where each of the basic cells comprise a pair of first p-channel transistor and first n-channel transistor, a plurality of interconnection regions each formed between two mutually adjacent ones of the basic cell columns, and specific cells buried in one or a plurality of predetermined ones of the interconnection regions, where each of the specific cells comprise at least a second p-channel transistor and a second n-channel transistor which constitute a transmission gate.

REFERENCES:
patent: 4668972 (1987-05-01), Sato et al.
patent: 4692783 (1987-09-01), Monma et al.

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