Gate array having I/O bias circuit formed from I/O cell

Details Gate array having I/O bias circuit formed from I/O cell Gate array having I/O bias circuit formed from I/O cell

1990-04-20

1991-08-13

Hudspeth, David

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

3072966, 3073031, 307455, 357 45, H01L 2172

Patent

active

050398849

ABSTRACT:
A gate array semiconductor integrated circuit includes a plurality of input/output cells, an input/output circuit, and a bias circuit. The plurality of input/output cells are arranged around an internal logic gate. The input/output circuit is formed by an aluminum master slice of the input/output cells and performs an input/output operation for the internal logic gate. The bias circuit is formed by the aluminum master slice of the input/output cells to supply a predetermined bias voltage to the input/output circuit.

REFERENCES:
patent: 4623802 (1986-11-01), Cline et al.
patent: 4631427 (1986-12-01), Mazumder et al.
patent: 4748488 (1988-05-01), Suzuki et al.
patent: 4751406 (1988-06-01), Wilson
patent: 4904887 (1990-02-01), Sugiyama et al.
patent: 4933576 (1990-06-01), Tamamura et al.
patent: 4942317 (1990-07-01), Tanaka et al.
Brackelmann et al., "A 150-ps. 9000-Gate ECL Masterslice", IEEE JSSC, vol, SC-20, No. 5, Oct. 1985, pp. 1032-1035.

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