Gate array having highly flexible interconnection structure

Active solid-state devices (e.g. – transistors – solid-state diode – Gate arrays – Having specific type of active device

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Details

257207, 257211, 257204, 257773, H01L 2710

Patent

active

058148442

ABSTRACT:
A basic cell structure of a gate array that allows wiring in a macro cell is implemented solely by using first layer metallic wires and entails neither performance deterioration nor an increase in sell size. The basic cell of the gate array comprises a pMOS transistor having two FETs connected in series to each other and an nMOS transistor also having two FETs also connected in series to each other. The pMOS transistor and the nMOS transistor are formed on a substrate and arranged in parallel to each other, and gate electrodes corresponding to the FETs are commonly provided for the pMOS transistor and the nMOS transistor. In this structure, a first auxiliary wire is provided between the gate electrodes on the same layer as the gate electrodes. A second auxiliary wire is provided between adjacent basic cells also on the same layer as the gate electrodes. Wiring in a macro cell can be completed by using the first and second auxiliary wires of different types to form a two-dimensional structure. That is, wiring can be completed solely by using the first layer metallic wires.

REFERENCES:
patent: 4692783 (1987-09-01), Monma et al.
patent: 4737836 (1988-04-01), Askin et al.
patent: 5083178 (1992-01-01), Otsu
patent: 5384472 (1995-01-01), Yin
patent: 5612553 (1997-03-01), Arakawa
patent: 5652441 (1997-07-01), Hashimoto et al.

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