Gate array device having macro cells for forming master and slav

Details Gate array device having macro cells for forming master and slav Gate array device having macro cells for forming master and slav

1989-05-09

1990-06-12

Hudspeth, David

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

3072722, 3073031, 307467, 357 45, H03K 19177

Patent

active

049335766

ABSTRACT:
A gate array device forms an arbitray logic circuit depending on interconnections formed thereon, and comprises a semiconductor chip having an approximate rectangular shape, an input terminal region including a plurality of input terminals formed at a peripheral portion of the semiconductor chip, an output terminal region including a plurality of output terminals formed at a peripheral portion of the semiconductor chip, and a macro cell region including a plurality of macro cells formed at a central portion of the semiconductor chip. The macro cells include first macro cells and second macro cells, where each of the first macro cells include a minimum number of elements for forming a master part of a master-slave flip-flop circuit and each of the second macro cells include at least a minimum number of elements for forming a slave part of the master-slave flip-flop circuit. The first macro cells and the second macro cells make macro cell pairs and are regularly arranged within the macro cell region.

REFERENCES:
patent: 4207556 (1980-06-01), Sugiyama et al.
patent: 4255672 (1981-03-01), Ohno et al.
patent: 4593205 (1986-06-01), Bass et al.
patent: 4611236 (1986-09-01), Sato
patent: 4750027 (1988-06-01), Asami
patent: 4760289 (1988-07-01), Eichelberger et al.
patent: 4851717 (1989-07-01), Yabe
patent: 4864381 (1989-09-01), Seeteldt et al.
patent: 4868630 (1989-09-01), Tanizawa et al.

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