Boots – shoes – and leggings
Patent
1988-01-14
1990-05-01
Lall, Parshotam S.
Boots, shoes, and leggings
364490, 364489, 364488, G06F 1560
Patent
active
049224417
ABSTRACT:
A gate array device includes a plurality of basic cell regions spaced apart from one another to thereby define a plurality of intermediate regions therebetween. Each intermediate region may serve either as a memory or function cell region or as an interconnection region at least partly. The memory cell region may be selectively defined as a ROM or a RAM by metallization. A test mode or a normal operating mode may be set selectively in accordance with a control signal. When the normal operating mode is set, an input terminal is operatively connected to a memory circuit through a logic circuit; whereas, when the test mode is set, the input terminal is directly connected to the memory circuit while bypassing the logic circuit. Also provided is a memory cell structure which can be defined as a RAM memory cell or as a ROM memory cell storing a selected binary data by metallization.
REFERENCES:
patent: 4613958 (1986-09-01), Culican et al.
patent: 4644187 (1987-02-01), Haji
patent: 4668972 (1987-05-01), Sato et al.
patent: 4675849 (1987-06-01), Kinoshita
patent: 4724531 (1988-02-01), Angleton et al.
patent: 4727493 (1988-02-01), Taylor, Sr.
patent: 4750027 (1988-06-01), Asami
patent: 4780846 (1988-10-01), Tanabe et al.
Fukushima Masanobu
Tsukagoshi Toshihiro
Yasui Takashi
Yoshioka Keiichi
Lall Parshotam S.
Ricoh & Company, Ltd.
Trans V. N.
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