Gate array circuit for decoding circuits

Details Gate array circuit for decoding circuits Gate array circuit for decoding circuits

1990-10-11

1991-08-27

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307463, 307469, 364716, 365231, H03K 17693, H03K 19003, H03K 19094, H03K 1704

Patent

active

RE0336769

ABSTRACT:
A decoder circuit for decoding different combinations of supplied original input address bits, comprising at least one predecode circuit responsive to the original input address bits for producing predecoded signal bits from the input address bits, and a plurality of decoder units including at least one decoder unit responsive to at least two different combinations of the original input address bits, wherein the decoder units comprises a decoder unit responsive to selected ones of the predecoded signal bits alone and a decoder unit responsive to at least one of the predecoded signal bits and at least one of the original input address bits.

REFERENCES:
patent: 4031477 (1977-06-01), Shaw
patent: 4069426 (1978-01-01), Hirasawa
patent: 4602347 (1986-07-01), Koyama
patent: 4625130 (1986-11-01), Murray
patent: 4675556 (1987-06-01), Bazes

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