Gate array cell having FETs of different and optimized sizes

Details Gate array cell having FETs of different and optimized sizes Gate array cell having FETs of different and optimized sizes

1990-04-03

1991-08-06

Jackson, Jr., Jerome

357 42, H01L 2702, H01L 2978

Patent

active

050381920

ABSTRACT:
A CMOS FET master slice integrated circuit (20) of the gate-array type implemented in a semiconductor logic chip, comprises a plurality of core cells (CELL1, CELL2, . . . ) arranged adjacent one another on a repetitive basis in a row direction to form horizontal stripe shaped functional gate region (21) of a determined height (H). Each core cell (e.g., CELL1) is comprised of four different sized devices: one small and one large NFET (N1.1, N2.1), thus one small and one larger PFET (P1.1, P2.1), that are disposed in a column direction. The NFETs have separate gate electrodes (GN1.1, GN2.1) to define individual devices, while the PFETs have preferably a common gate electrode (GP1) to define a single device. The relative size of NFETs and PFETs have been optimized to provide the required functionality to the latches and to ensure the balanced rise and fall delays in a maximum of basic logic circuits of the chip. As a result, the use of such core cells, allows that complex logic functions, such as latches, can be implemented in gate arrays that have a density and performance comparable with standard cell circuits. In addition, the use of these core cells also permits optimization of other basic logic circuits (INV, NOR, . . . ) that are used in critical logic paths and clock distribution trees, where balanced delays are highly desirable.

REFERENCES:
patent: 4692783 (1987-09-01), Monma et al.
Article entitled "A 240k Transistor CMOS Array With Flexible Allocation of Memory and Channels," by H. Takahashi et al., in IEEE Journal of Solid-State Circuits, vol. SC-20, No. 5, pp. 1012-1017; dated Oct. 1985.
Article entitled "A Triple-level Wired 24k-gate CMOS Gate Array," by T. Saigo et al., in IEEE Journal of Solid-State Circuits; vol. SC-20, No. 5, pp. 1005-1011, dated Oct. 1985.
Article entitled "Fujitsu Ups and Gate-array Ante: 90,000 Usable Gates," by B. C. Cole, in Electronics; vol. 61, No. 7; pp. 77-78, date Mar. 31, 1988.
Article entitled "A 6K-gate CMOS Gate Array," by H. Tago et al., in IEEE Journal of Solid-Sate Circuits; vol. SC-17, No. 5, pp. 907-912, dated Oct. 1982.

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