Gate array arrangement

Details Gate array arrangement Gate array arrangement

1988-04-18

1989-03-07

James, Andrew J.

357 68, 357 40, 357 71, H01L 2710, H01L 2715

Patent

active

048110736

ABSTRACT:
A gate array arrangement formed on a semiconductor chip includes a plurality of I/O cells aligned along the four sides of the chip and a plurality of basic cells aligned in a plurality of rows extending parallelly to each other. A ground bus line and a power bus line extend in a space between the I/O cells and basic cells. The lines from the I/O cells are connected to the bus lines, and lines from basic cells are connected to bus lines. In this manner, the power supply lines between the I/O cells and basic cells are connected indirectly through the bus line, thereby allowing the determination of pitch of the I/O cells and pitch of basic cells independently of each other.

REFERENCES:
patent: 4393464 (1983-07-01), Knapp et al.
patent: 4523106 (1985-06-01), Tanizawa et al.
patent: 4562453 (1985-12-01), Noguchi et al.
patent: 4568961 (1986-02-01), Noto
Nakaya, M. et al., "High-Speed MOS Gate Array", IEEE Trans. on Elec. Dev., Aug. 1980, pp. 1665-1670.

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