Active solid-state devices (e.g. – transistors – solid-state diode – Gate arrays – With particular power supply distribution means
Reexamination Certificate
2000-06-06
2003-09-09
Eckert, George (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Gate arrays
With particular power supply distribution means
C257S203000, C257S208000
Reexamination Certificate
active
06617621
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates generally to integrated circuits. More specifically, it provides a new architecture, method of manufacturing and method of design for integrated circuits with multiple metal layers.
In today's rapidly changing environment, time to market is one of the key challenges of integrated circuit designers. Thus, methodologies and architectures have been developed over the years to speed up the time it takes to design and manufacture an integrated circuit. Two methods that have been used extensively in the past are standard cell and gate array technologies. Though these methods have provided some benefits, the benefits have come at a cost.
In standard cell technology, a physical library of commonly used functional blocks such as NAND, NOR, flip-flops, multiplexors, counters, and the like are pre-designed for use by the designer. The designer simply picks the functional blocks needed for the design and describes their interconnections. Then, the design is automatically placed and routed with software tools. This provides an improvement over full custom design in which the designer does not have a ready and pre-verified library of cells available to him. However, in the standard cell methodology, each functional block has its own unique geometries of active, gate and metal layers, so fabrication of a standard cell integrated circuit requires processing of each layer after completion of the functional design. Moreover, each layer requires a different mask to project the pattern on the silicon wafer. Lately, the cost of masks has become very high and is projected to exceed $500,000 per mask set in the near future. Hence standard cell design flow is becoming simply unacceptable to many designers in terms of both time and cost.
To solve some of these shortcomings, gate array technology became popular for faster turn-around time and reduced mask cost. Like standard cell design, gate array technology also comprises a library of predesigned and preverified logic blocks, but in gate arrays the logic blocks are built upon from the same basic unit (called a “core cell” or “basic cell”) consisting of fixed active (diffusion) and gate level geometries. Different functions are created by personalizing the metal layers only. Consequently, only the metal layers need to be processed after completion of a design based on gate array technology. Many times the gate array design approach is known as a metal programmable design approach. The fabrication of a gate array thus has two phases, a pre-design phase in which the non-metal layers are fabricated ahead of design completion, and a post design phase in which the design specific metal layers are fabricated after the design is completed. This can shave several weeks off the manufacturing cycle compared with full custom or standard cell design. As the cost of manufacturing masks has increased with decreasing geometries, the lower mask cost has become a second significant benefit of gate arrays.
On the other hand, gate arrays have two distinct disadvantages in comparison with standard cell designs. First, the height of gate array cells is typically 20% to 30% larger than standard cells. This is because the gate arrays can only use metal layers to interconnect the transistors, whereas the standard cell layouts are free to use diffusion and gate electrode layers for some of the connections. This limitation is especially evident in the design of complex synchronous cells such as flip-flops. As a result, the gate array densities are significantly lower than those of standard cells, resulting in a more expensive silicon die. The second disadvantage of gate arrays is a significantly higher power dissipation that results from the fact that all transistors are generally made of the same size unlike standard cell designs in which the transistors are optimized for speed, power, and density. Moreover, synchronous circuits such as flip-flops and the like exacerbate this problem since they are switched at every clock cycle. U.S. Pat. Nos. 5,341,041 and 5,289,021 disclose a new type of gate array architecture that includes three different sizes of transistors in a core cell. The core cell consists of two types of subcells. One subcell includes small and medium sized transistors and a second subcell includes large transistors. The choice of different sized transistor permits a better optimization of the speed and power of complex cells such as flip-flops. However, since a particular design does not necessarily use the three different transistor sizes in the proportion they are provided, many transistors are often wasted. Further, the inclusion of several different transistors makes the cell significantly larger, resulting in lower gate density. Other gate array structures that include multiple transistor sizes are disclosed in U.S. Pat. Nos. 4,816,887; 5,038,192 and 4,668,972. However, none of those approaches provide a metal programmable design with density and power that are comparable to standard cell.
Another major problem faced by integrated circuit designers is the routing of global signals. A lot of design time is spent minimizing the clock skew and power dissipation. As the minimum geometries used in the design of integrated circuits reach 0.25 micrometer and smaller, the global routes, such as clock, reset, test and power distribution can account for over 40% of the total metal routing resources as well as the power dissipation of a design. The current design methodologies disregard routing of these global nets in the initial placement of the logic cells. Typically, the cells are placed with the primary objective of reducing the wire length of signal interconnects between different logic cells. Consequently, a long clock signal has to be routed to all the flip-flops, resulting in large clock skew and high power dissipation. Also, since these global signals are routed after initial placement, the original placement is perturbed by the global signals, resulting in a time consuming, iterative design flow.
Accordingly, improvements to the state of the art are needed to solve the global routing and time to market problems of custom, standard cell, and gate array technologies, while still allowing high density design.
SUMMARY OF THE INVENTION
The present invention provides a gate array architecture and method of design for integrated circuits that provides fast design and manufacturing. These new gate arrays feature density and power comparable to standard cell designs, while retaining faster manufacturing and lower mask cost over standard cell.
According to an aspect of the present invention, the fabrication of an application specific integrated circuit (ASIC) has two steps, a pre-design fabrication process and a post-design fabrication process. In the pre-design fabrication process, the silicon wafer is prefabricated with standardized core cells without the design-specific customization of the functional aspect of the design. In the post-design fabrication steps the design-specific customization is completed using only the upper metal layers to quickly implement a specific design intent.
In a specific embodiment of the present invention, the predesign fabrication process extends up through the third level of metal (M
1
, M
2
, and M
3
), though other embodiments may prefabricate more layers without departing from the spirit, intent, and the scope of the present invention. A designer then provides design-specific information to customize the design for a particular application. This customization is done using only the higher metal layers—in the specific embodiment, metal layers four and five (M
4
and M
5
). Accordingly, fabrication after design completion need only be completed for the upper layers, further reducing the turn around time and the mask costs for fabrication as compared to a conventional all-metal programmable gate array or conventional standard cells.
According to another aspect of the present invention, a method of designing an integrated circuit is provided. The method includes forming tr
Breid Duane G.
Colwell Michael J.
Gheewala Tushar R.
Sherlekar Deepak D.
Allen Kenneth R.
Eckert George
Townsend and Townsend / and Crew LLP
Virage Logic Corporation
LandOfFree
Gate array architecture using elevated metal levels for... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Gate array architecture using elevated metal levels for..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Gate array architecture using elevated metal levels for... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3065931