Gate array architecture

Details Gate array architecture Gate array architecture

2001-07-10

2004-06-22

Pham, Long (Department: 2814)

Semiconductor device manufacturing: process

Making device array and selectively interconnecting

C438S587000, C438S598000, C257S202000

Reexamination Certificate

active

06753209

ABSTRACT:

BACKGROUND
1. Field
The present invention is related to integrated circuit chips and, more particularly, to gate array architectures for integrated circuit chips.
2. Background
Gate array architectures are commonly used for many types of integrated circuit designs. In this context, the term gate array architecture refers to a repeated pattern of transistors embedded in a semiconductor or silicon substrate. Typically, such architectures are employed by using a “library” that comprises unique metallization patterns to create individual cells. Such gate array architectures and libraries are commonly employed in connection with computer-aided design (CAD) and/or computer-aided manufacturing (CAM) techniques. Employing a gate array architecture stands in contrast to the custom design of the layout of transistors on a silicon or semiconductor substrate, which is also accomplished using CAD/CAM techniques. Use of gate array architectures offers the advantage of quicker or shorter fabrication and throughput time, lower costs and ease in making fixes or logic changes after a chip design has already been completed. Unfortunately, gate array architectures also have a number of shortcomings that make them less attractive for some types of applications. Typically, gate arrays or gate array architectures are not as dense, have higher power consumption, and offer lower performance than custom circuits designed using alternative approaches. A need, therefore, exists for a gate array architecture that addresses at least some of these limitations.
SUMMARY
Briefly, in accordance with one embodiment of the invention, an integrated circuit includes: a gate array architecture. The gate array architecture includes a semiconductor substrate having a plurality of N-type diffusion regions and P-type diffusion regions. The diffusion regions have partially overlying polysilicon landing sites to form N-type and P-type transistors. The regions are relatively sized to form two distinct transistor sizes, smaller N- and P-type transistors and larger N-and P-type transistors.


REFERENCES:
patent: 4611236 (1986-09-01), Shaw
patent: 4692783 (1987-09-01), Monma et al.
patent: 4816887 (1989-03-01), Sato
patent: 5055716 (1991-10-01), El Gamel
patent: 5068548 (1991-11-01), El Gamel
patent: 5095356 (1992-03-01), Ando et al.
patent: 5117277 (1992-05-01), Yuyama et al.
patent: 5187556 (1993-02-01), Nariishi et al.
patent: 5289021 (1994-02-01), El Gamel
patent: 5341041 (1994-08-01), El Gamel
patent: 5510636 (1996-04-01), Murata
patent: 5563430 (1996-10-01), Hasimoto et al.
patent: 5576645 (1996-11-01), Farwell
patent: 5591995 (1997-01-01), Shaw
patent: 5684311 (1997-11-01), Shaw
patent: 5698873 (1997-12-01), Colwell et al.
patent: 5780883 (1998-07-01), Tran et al.
patent: 5789966 (1998-08-01), Bachade
patent: 5796128 (1998-08-01), Tran et al.
patent: 5796129 (1998-08-01), Mizuno
patent: 5932900 (1999-08-01), Lin et al.
patent: 5969379 (1999-10-01), Thompson et al.
patent: 2000137060 (2000-05-01), None
SiArc Base Array, SPG Central Logic Engineering, Intel Corporation, 1 pg.

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