Gate array and manufacturing method of semiconductor memory devi

Details Gate array and manufacturing method of semiconductor memory devi Gate array and manufacturing method of semiconductor memory devi

1992-03-11

1993-07-13

Thomas, Tom

Fishing, trapping, and vermin destroying

437173, 437195, H01L 2170

Patent

active

052273245

ABSTRACT:
A gate array is provided which includes a semiconductor substrate having a main surface. The main surface includes a cell region and a channel region adjacent to the cell region. A cell column including a plurality of basic cells arranged regularly is provided in the cell region. A first interconnecting line is provided in the channel region for connecting the basic cells. In accordance with the gate array, as the first interconnecting line is formed in the channel region in advance for connecting the basic cells, it is not necessary to form a first interconnecting line when manufacturing a semiconductor integrated circuit device. Accordingly, the time period for development of a semiconductor integrated circuit device can be reduced as compared with a case where conventional basic cells are used.

REFERENCES:
patent: 4500906 (1985-02-01), Ohno et al.
patent: 4716452 (1987-12-01), Kondoh et al.
patent: 4745084 (1988-05-01), Rowson et al.
patent: 5031018 (1991-07-01), Shirato et al.

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