1986-10-23
1987-09-08
Larkins, William D.
357 41, 357 45, 357 20, H01L 2704, H01L 2978
Patent
active
046927832
ABSTRACT:
A gate array is disclosed having a plurality of basic cells each comprising a transistor whose gm is as low as one fifth to one twentieth that of the transistors in a conventional gate array. The low gm is provided by reducing the W/L ratio of the gate region of the transistor. The basic cell having the transistor of the low gm is formed to replace the conventional basic cell at a specified position in a specified basic cell array. The transistor of low gm reduces the number of basic cells necessary for forming a delay circuit, and elminates the need for an external resistance component which was formerly required when a pull-up or pull-down circuit or a monostable multivibrator was formed in the gate array.
REFERENCES:
patent: 3508084 (1970-04-01), Warner
patent: 4278897 (1981-07-01), Ohno et al.
patent: 4575745 (1986-03-01), Sharma
Electronic Engineering, vol. 54, No. 663, Mar. 1982, pp. 53-57, London, G.B. "Designing with ULA`s; Part 1: Technology Circuit Elements".
Ishiguro Masato
Kawano Tetsuo
Monma Hideo
Fujitsu Limited
Larkins William D.
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