Gate addressing system for logic simulation machine

Details Gate addressing system for logic simulation machine Gate addressing system for logic simulation machine

1991-01-29

1993-09-14

Trans, Vincent N.

Boots, shoes, and leggings

364488, 364578, G06F 1560

Patent

active

052455491

ABSTRACT:
A gate addressing system of a logic simulation machine performs translation from data of a circuit design data base to circuit data for the logic simulation machine. The system numbers each input terminal of a circuit and each gate of said circuit without using numbers corresponding to the number of fanout gates minus one to which an output signal of an input terminal or a gate is applied between the numbers of one input terminal and another input terminal, one input terminal and one gate, one gate and another gate or one gate and one input terminal. It starts a list of numbers of fanout gates of each input terminal or each gate at an address as the number assigned to said input terminal and gate in a table representing connection relationships among input terminals and gates and among gates.

REFERENCES:
patent: 4816999 (1989-03-01), Berman et al.
patent: 4899273 (1990-02-01), Omoda et al.
patent: 4924429 (1990-05-01), Kurashita et al.
patent: 5051938 (1991-09-01), Hyduke
patent: 5051941 (1991-09-01), Takamine et al.

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