Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2001-12-21
2004-02-03
Lam, David (Department: 2818)
Static information storage and retrieval
Floating gate
Particular connection
C365S185050, C365S185330
Reexamination Certificate
active
06687158
ABSTRACT:
FIELD OF THE INVENTION
The invention relates generally to the field of electronic memory design, and in particular to techniques for improving performance in a NAND type flash memory.
BACKGROUND OF THE INVENTION
Demand for flash memory is growing rapidly due to the wide range of portable and embedded products with increased storage requirements. A flash memory can replace a bulk storage medium such as a hard disk, and is used in, for example, digital cameras, and voice mail systems. A NAND Flash memory cell array typically includes several single bit storage transistors, i.e., memory cells, in series. These memory cells are organized into pages. For example, a page may include 512 bytes (4096 bits). There are several pages per block, where erasing is done on a per block basis. Read access to the memory cell array is by page. Given a starting page address, sequential pages may be read out quickly, for example, with a 50 nsec cycle time per byte. Access to a byte within a page is done sequentially. Writing a page to the memory cell array is done in two steps: first, the address and data are written to an internal register, i.e., page buffers; and second, a special command initiates the writing, i.e., programming, of the data in the internal register to the non-volatile memory cell array. The writing of the data is done only on a per page basis. While the read access is fast, write time is slow, for example 200 &mgr;sec.
FIG. 1
is a simplified architecture of a typical prior art NAND type flash memory device. The NAND Flash memory architecture
110
includes a State Machine
112
, a Command Register
114
, and an Address Register
116
, a Status Register
118
, a Memory Array
120
, a Y Decoder
122
, Page Buffers
124
, a X-Decoder
126
, and I/O Registers
132
. The I/O Registers
132
receive input/output to the memory device through the I/O Ports
134
. The I/O Ports
134
receive a page address, which is sent to the Address Register
116
. The I/O Registers
132
next receive data for that address. This data is sent to the Y-Decoder
122
and written in Page Buffers
124
, for example, page
130
, using the address from the Address Register
116
via the X-Decoder
126
. Each rising edge of a write enable bar (WEbar) signal
136
writes one byte of data from the I/O Registers
134
to eight one-bit page buffers in Page Buffers
124
. A programming control signal from the Ready/Busy Line (not shown) then writes the data in the Page Buffers
124
to the memory cells in Memory Array
120
, e.g., page
130
. To read a page, e.g. page
130
, the page address in Page Address Register
116
is sent to the X-Decoder
126
to access the page, and write it to the Page Buffers
124
for reading. The Read Enable bar (REbar) signal
138
is used to read out the data to the I/O Registers
132
.
FIG. 2
is a simplified and expanded block diagram of a typical Memory Array
120
of the prior art.
FIG. 2
shows a plurality of blocks of data, for example blocks
212
,
214
,
218
,
222
and
220
. In block
212
there are one or more pages, for example, page
—
0
240
and page_i
242
. Page_i
242
includes 512 memory cells, e.g.,
244
,
246
, and
248
, where each memory cell stores one bit. Each memory cell within a page is programmed by 512 parallel bit lines (BL), e.g., BL
0
230
for cell
244
, BL
1
232
for cell
246
, and BL
511
234
for cell
248
. All 512 memory cells in a page, e.g., Page_i
240
, are programmed concurrently. Each block, e.g., block
212
has an associated seven other blocks, e.g.,
214
,
218
, and five other blocks (not shown). This group of blocks is programmed (and read) in parallel, so that bytes of data, rather than bits of data, may be accessed per page, e.g., 512 bytes for Page_i
242
. Thus, each block e.g., block
212
, has a plurality of pages, e.g., Page_i
242
, where each page, e.g., Page_i
242
, has 512 bits concurrently programmed by bit lines BL
0
230
to BL
511
234
. And each block is eight bits deep, e.g., blocks
212
to
218
, so that Page_i has 512 bytes programmed (and read) in parallel.
FIG. 3
is an example of an expanded view
310
of the Page Buffers
124
for 512 bits. For example, for page Page_i
242
there are 4096 (512×8) page buffers for a 512-byte page. Page Buffer
312
is an example page buffer for one bit. The Page Buffer
312
is one Page Buffer of the plurality of Page Buffers
124
in FIG.
1
. The Page Buffer
312
includes a data line, DATA
1
314
that receives one bit of data from I/O Registers
132
via the Y-Decoder
122
of
FIG. 1
upon the rising edge of WEbar
136
. DATA
1
314
is stored using a “keeper,” having back-to-back inverters, i.e., inverter
334
and inverter
336
. When the signal POMON
322
is high, transistor
332
turns on, and when BL CONTROL
326
is high, the value stored in the keeper is then sent to bit line BL
1
232
and used to program, for example, memory cell
246
in Page_i
242
of FIG.
2
.
Also shown in
FIG. 3
are PMOS transistor
330
, NMOS transistors
338
and
340
, SET signal
324
and PBIAS signal
320
. These components are related to a method for verifying the complete erasure of the memory cells (e.g.,
244
,
246
,
248
) during a block erase operation, as taught, for example, by U.S. Pat. No. 6,009,014, and do not form part of the present invention. After a block erase operation, the keeper formed by inverters
334
and
336
is placed in a set state (output of inverter
334
high) by grounding DATA
1
signal
314
while PGMON signal
322
is low. BLCONTROL signal
326
is then set high, thereby coupling pagebuffer
310
to bit line BL
1
(
232
) via a pass transistor
342
, and thereby to a set of memory cells to be tested. PBIAS signal
320
is then activated to cause transistor
330
to generate a test current, which is directed to the memory cells by way of the conducting pass transistor
342
. If the memory cells have been fully erased, the test current will be fully conducted by the cells. However, if the memory cells are not fully erased, the test current will accumulate at the gate of NMOS transistor
338
, causing it to turn on and be conductive. As the next step in the erase verification step, SET signal
324
is momentarily pulsed to a high state, causing NMOS transistor
340
to conduct. If NMOS transistor
338
is also conducting at this time (because the memory cells are not fully erased), the input of inverter
336
will be grounded and the keeper is placed in a reset state (output of inverter
334
low). After the pulsing of SET signal
324
, the keeper may be read via DATA
1
line
314
to determine if it has been reset, indicating incomplete erasure.
FIG. 4
is a simplified timing diagram
410
showing the writing process of a typical NAND type flash memory of the prior art. An example NAND Flash memory device is the Advanced Micro Devices (AMD) C-MOS 3.0 volt-only NAND Flash Memory Am3LV0I28D. The write enable bar (WEbar)
412
shows a plurality of write pulses, e.g., rising edges
414
,
416
, and
418
. The data
420
, for example DATA
0
422
, DATA
1
424
, and DATA
511
426
, is read from the I/O Registers
132
and written into the Page Buffers
124
at each rising edge of WEbar
412
e.g.,
414
,
416
,
418
. For example, DATA
0
422
(one byte) is written into its eight page buffers on the rising edge of
414
of WEbar
412
. This is done for the 512 bytes. Next the Ready/Busy Line (RIB)
430
transitions from high to low
432
to start the programming of the data in the Page Buffers
124
into a page, e.g. page 130, in Memory Array
120
(FIG.
1
). The programming time
434
is a pulse typically lasting approximately 200-250 microseconds. From
FIG. 4
, for each data write of a page into the memory array, there is a series of write enable pulses to input data into the page buffers, followed by a programming pulse to program the page into the memory array. The problem is that this sequential process of input data—program page, input next data—program next page, etc., for writing a plurality of sequential pages is time consuming.
Therefore with
Fujitsu Limited
Lam David
Sheppard Mullin Richter & Hampton LLP
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