Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Patent
1996-08-08
1998-12-22
Dang, Trung
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
438424, 438692, 438788, H01L 2176
Patent
active
058518991
ABSTRACT:
Described is a method for filling shallow trench isolation (STI) trenches in a semiconductor substrate of an integrated circuit with an insulating material and planarizing the resulting structure to the level of adjacent portions of the integrated circuit. The method comprises forming trenches in the non-active regions of a semiconductor substrate, depositing a layer of oxide in the trenches and over the surface of the semiconductor substrate, and removing the oxide from the active areas of the integrated circuit structure, leaving oxide-filled shallow trench isolation structures having a substantially planar topography with respect to the rest of the integrated circuit structure.
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Chatterjee et al. "A Shallow Trench Isolation Study for 0.25/0.18 Mm Cmos Technologies and Beyond"; Symposium on VLSI Technology Digest of Technical Papers ; Jun. 1996 ; 156-157.
Braden Stanton C.
Dang Trung
Siemens Aktiengesellschaft
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