Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Patent
1999-01-07
2000-08-08
Pham, Long
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
438425, 438427, 438435, 438789, H01L 2176
Patent
active
061001635
ABSTRACT:
A method for filling a trench within a silicon substrate. There is first provided a silicon substrate having a trench formed therein. There is then oxidized thermally the silicon substrate to form within the trench a thermal silicon oxide trench liner layer. There is then treated the thermal silicon oxide trench liner layer by exposure to a plasma formed from a gas composition which upon plasma activation simultaneously supplies an active nitrogen containing species and an active oxygen containing species to form a plasma treated thermal silicon oxide trench liner layer. There is then formed upon the plasma treated thermal silicon oxide trench liner layer a conformal silicon oxide intermediate layer formed through a plasma enhanced chemical vapor deposition (PECVD) method employing a silane silicon source material. Finally, there is then formed upon the conformal silicon oxide intermediate layer a gap filling silicon oxide trench fill layer through an ozone assisted sub-atmospheric pressure thermal chemical vapor deposition (SACVD) method employing an ozone oxidant and a tetra-ethyl-ortho-silicate (TEOS) silicon source material.
REFERENCES:
patent: 5508221 (1996-04-01), Kamiyama
patent: 5536681 (1996-07-01), Jang et al.
patent: 5726090 (1998-03-01), Jang et al.
patent: 5731241 (1998-03-01), Jang et al.
Chen Ying-Ho
Jang Syun-Ming
Yu Chen-Hua
Ackerman Stephen B.
Pham Long
Saile George O.
Taiwan Semiconductor Manufacturing Company
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