Galois field multiplier array for use within a finite field...

Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed

Reexamination Certificate

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Reexamination Certificate

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07403964

ABSTRACT:
A Galois field multiplier array includes a 1stregister, a 2ndregister, a 3rdregister, and a plurality of multiplier cells. The 1stregister stores bits of a 1stoperand. The 2ndregister stores bits of a 2ndoperand. The 3rdregister stores bits of a generating polynomial that corresponds to one of a plurality of applications (e.g., FEC, CRC, Reed Solomon, et cetera). The plurality of multiplier cells is arranged in rows and columns. Each of the multiplier cells outputs a sum and a product and each cell includes five inputs. The 1stinput receives a preceding cell's multiply output, the 2ndinput receives at least one bit of the 2ndoperand, the 3rdinput receives a preceding cell's sum output, a 4thinput receives at least one bit of the generating polynomial, and the 5thinput receives a feedback term from a preceding cell in a preceding row. The multiplier cells in the 1strow have the 1stinput, 3rdinput, and 5thinput set to corresponding initialization values in accordance with the 2ndoperand.

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patent: 6606342 (2003-08-01), Banister
patent: 6687725 (2004-02-01), Chen et al.
patent: 6988118 (2006-01-01), Chiou

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