Galois field arithmetic unit for use within a processor

Details Galois field arithmetic unit for use within a processor Galois field arithmetic unit for use within a processor

2007-12-25

2007-12-25

Ngo, Chuong D. (Department: 2193)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

C714S784000

Reexamination Certificate

active

10460599

ABSTRACT:
A Galois field arithmetic unit includes a Galois field multiplier section and a Galois field adder section. The Galois field multiplier section includes a plurality of Galois field multiplier arrays that perform a Galois field multiplication by multiplying, in accordance with a generating polynomial, a 1stoperand and a 2ndoperand. The bit size of the 1stand 2ndoperands correspond to the bit size of a processor data path, where each of the Galois field multiplier arrays performs a portion of the Galois field multiplication by multiplying, in accordance with a corresponding portion of the generating polynomial, corresponding portions of the 1stand 2ndoperands. The bit size of the corresponding portions of the 1stand 2ndoperands corresponds to a symbol size of symbols of a coding scheme being implemented by the corresponding processor.

REFERENCES:
patent: 5642367 (1997-06-01), Kao
patent: 5768168 (1998-06-01), Im
patent: 5999959 (1999-12-01), Weng et al.
patent: 7003715 (2006-02-01), Thurston

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