Galois field arithmetic logic unit circuit

Details Galois field arithmetic logic unit circuit Galois field arithmetic logic unit circuit

1997-12-24

1999-12-14

Mai, Tan V.

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

G06F 700

Patent

active

060030577

ABSTRACT:
A Galois Field arithmetic logic unit (GF ALU) circuit (200) that generates a GF product of size M includes a first and a second input field element register (205, 210), a result field element register (215), a plurality, I, of subfield sets of logic gates (255, 260, 265), a plurality, S, of extension sets of logic gates (270, 275), and 3M switches (135). M is equal to S multiplied by I. A Galois Field of size M, S, and I each has an optimal normal basis. The first and second input field element registers (205, 210) are alternately coupled to the result field element register (215) by the I subfield sets of logic gates (255, 260, 265) in a first configuration and by the S extension sets of logic gates (270, 275) in a second configuration. The 3M switches (135) alternate the first and second configurations.

REFERENCES:
patent: 5227992 (1993-07-01), Lee et al.
patent: 5787028 (1998-07-01), Mullin

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