Gallium nitride semiconductor structure including laterally...

Details Gallium nitride semiconductor structure including laterally... Gallium nitride semiconductor structure including laterally...

1998-02-27

2003-08-19

Lee, Eddie (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Specified wide band gap semiconductor material other than...

C257S103000, C257S615000

Reexamination Certificate

active

06608327

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to microelectronic devices and fabrication methods, and more particularly to gallium nitride semiconductor devices and fabrication methods therefor.
BACKGROUND OF THE INVENTION
Gallium nitride is being widely investigated for microelectronic devices including but not limited to transistors, field emitters and optoelectronic devices. It will be understood that, as used herein, gallium nitride also includes alloys of gallium nitride such as aluminum gallium nitride, indium gallium nitride and aluminum indium gallium nitride.
A major problem in fabricating gallium nitride-based microelectronic devices is the fabrication of gallium nitride semiconductor layers having low defect densities. It is known that one contributor to defect density is the substrate on which the gallium nitride layer is grown. Accordingly, although gallium nitride layers have been grown on sapphire substrates, it is known to reduce defect density by growing gallium nitride layers on aluminum nitride buffer layers which are themselves formed on silicon carbide substrates. Notwithstanding these advances, continued reduction in defect density is desirable.
It is also known to fabricate gallium nitride structures through openings in a mask. For example, in fabricating field emitter arrays, it is known to selectively grow gallium nitride on stripe or circular patterned substrates. See, for example, the publications by coinventor Nam et al. entitled “Selective Growth of GaN and Al
0.2
Ga
0.8
N on GaN/AlN/6H—SiC(0001) Multilayer Substrates Via Organometallic Vapor Phase Epitaxy”, Proceedings of the Materials Research Society, December 1996, and “Growth of GaN and Al
0.2
Ga
0.8
N on Patterened Substrates via Organometallic Vapor Phase Epitaxy”, Japanese Journal of Applied Physics., Vol. 36, Part 2, No. 5A, May 1997, pp. L-532-L535. As disclosed in these publications, undesired ridge growth or lateral overgrowth may occur under certain conditions.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide improved methods of fabricating gallium nitride semiconductor layers, and improved gallium nitride layers so fabricated.
It is another object of the invention to provide methods of fabricating gallium nitride semiconductor layers that can have low defect densities, and gallium nitride semiconductor layers so fabricated.
These and other objects are provided, according to the present invention, by fabricating a gallium nitride semiconductor layer by laterally growing an underlying gallium nitride layer to thereby form a first laterally grown gallium nitride semiconductor layer, and laterally growing the first laterally grown gallium nitride layer to thereby form a second laterally grown gallium nitride semiconductor layer. Microelectronic devices may then be formed in the second laterally grown gallium nitride semiconductor layer.
More specifically, in a preferred embodiment, a gallium nitride semiconductor layer is fabricated by masking an underlying gallium nitride layer with a first mask that includes a first array of openings therein and growing the underlying gallium nitride layer through the first array of openings and onto the first mask, to thereby form a first overgrown gallium nitride semiconductor layer. The first overgrown layer is then masked with the second mask that includes a second array of openings therein. The second array of openings is laterally offset from the first array of openings. The first overgrown gallium nitride layer is then grown through the second array of openings and onto the second mask, to thereby form a second overgrown gallium nitride semiconductor layer. Microelectronic devices may then be formed in the second overgrown gallium nitride semiconductor layer.
It has been found, according to the present invention, that although dislocation defects may propagate vertically from the underlying gallium nitride layer to the grown gallium nitride layer above the first mask openings, the first overgrown gallium nitride layer is relatively defect-free. Moreover, since the second array of mask openings is laterally offset from the first array of mask openings, the relatively defect-free overgrown first gallium nitride layer propagates through the second array of openings and onto the second mask. Accordingly, high performance microelectronic devices may be formed in the second overgrown gallium nitride semiconductor layer.
According to another aspect of the present invention, the second overgrown gallium nitride semiconductor layer is overgrown until the second overgrown gallium nitride layer coalesces on the second mask, to form a continuous overgrown monocrystalline gallium nitride semiconductor layer. The entire continuous overgrown layer can thus be relatively defect-free compared to the underlying gallium nitride layer.
The first and second gallium nitride semiconductor layers may be grown using metalorganic vapor phase epitaxy (MOVPE). Preferably, the openings in the masks are stripes that are oriented along the <1{overscore (1)}00> direction of the underlying gallium nitride layer. The overgrown gallium nitride layers may be grown using triethylgallium (TEG) and ammonia (NH
3
) precursors at 1000-1100° C. and 45 Torr. Preferably, TEG at 13-39 &mgr;mol/min and NH
3
at 1500 sccm are used in combination with 3000 sccm H
2
diluent. Most preferably, TEG at
26 &mgr;mol/min, NH
3
at 1500 sccm and H
2
at 3000 sccm at a temperature of 1100° C. and 45 Torr are used. The underlying gallium nitride layer preferably is formed on a substrate, which itself includes a buffer layer such as aluminum nitride, on a substrate such as 6H—SiC(0001).
Gallium nitride semiconductor structures according to the present invention include an underlying gallium nitride layer, a first lateral gallium nitride layer that extends from the underlying gallium nitride layer and a second lateral gallium nitride layer that extends from the first lateral gallium nitride layer. A plurality of microelectronic devices are provided in the second lateral gallium nitride layer.
In a preferred embodiment, gallium nitride semiconductor structures according to the present invention include an underlying gallium nitride layer and a first mask that includes a first array of openings therein, on the underlying gallium nitride layer. A first vertical gallium nitride layer extends from the underlying gallium nitride layer through the first array of openings. A first lateral gallium nitride layer extends from the vertical gallium nitride layer onto the mask, opposite the underlying gallium nitride layer. A second mask on the first lateral gallium nitride layer includes a second array of openings therein that are laterally offset from the first array of openings. A second vertical gallium nitride layer extends from the first lateral gallium nitride layer and through the second array of openings. A second lateral gallium nitride layer extends from the second vertical gallium nitride layer onto the second mask, opposite the first lateral gallium nitride layer. A plurality of microelectronic devices including but not limited to optoelectronic devices and field emitters, are formed in the second vertical gallium nitride layer and in the second lateral gallium nitride layer.
Preferably, the second lateral gallium nitride layer is a continuous monocrystalline gallium nitride semiconductor layer. The underlying gallium nitride layer includes a predetermined defect density, and the second vertical and lateral gallium nitride semiconductor layers are of lower defect density than the predetermined defect density. Accordingly, continuous low defect density gallium nitride semiconductor layers may be produced, to thereby allow the production of high-performance microelectronic devices, using laterally offset masks.


REFERENCES:
patent: 4127792 (1978-11-01), Nakata
patent: 4522661 (1985-06-01), Morrison et al.
patent: 4651407 (1987-03-01), Bencuya
patent: 4865685 (1989-09-01), Palmour
patent: 4876210 (1989-10-01), Barnett et al.
patent: 4912064 (1990-03-01), Kong et

Affiliated with

Also associated with

Rating

Gallium nitride semiconductor structure including laterally... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Gallium nitride semiconductor structure including laterally..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Gallium nitride semiconductor structure including laterally... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3108647