Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons
Patent
1985-12-05
1987-01-27
Anagnos, Larry N.
Electrical transmission or interconnection systems
Nonlinear reactor systems
Parametrons
307303, 307304, 307448, H03K 19094, H03K 1920, H03K 19017
Patent
active
046396217
ABSTRACT:
A gallium arsenide NAND gate is connected between a power source and a ground potential. The gate is comprised of a load transistor of a normally-on type field effect transistor having an output terminal and a drain connected to the power source, a first driver transistor of a normally-off type field effect transistor having a gate electrode as a first input terminal and a source-to-drain current path series-connected to that of the load transistor, and a second driver transistor of two normally-off type field effect transistors having a common gate electrode for a second input terminal and source-to-drain current paths series-connected between the power source and the ground potential through the series-connected first driver transistor and load transistor. The normally-off type field effect transistors are parallel-connected to each other so as to equally constitute a single driver transistor as the second driver transistor.
REFERENCES:
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patent: 4300064 (1981-11-01), Eden
patent: 4430583 (1984-02-01), Shoji
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Kobayashi et al, "A 6K-Gate CMOS Gate Array"; IEEE ISSCC 1982; 2/11/1982 Digest of Technical Papers; pp. 174-175.
IEEE Transactions on Electron Devices, vol. ED-31, No. 2, p. 144 (1984), "A Gallium Arsenide SDFL Gate Array with On-Chip RAM"; Tho T. Vu et al; Feb. 1984.
IEEE Journal of Solid-State Circuits, vol. SC-19, No. 5, p. 728 (1984), "A Gallium Arsenide Configurable Cell Array Using Buffered FET Logic"; R. N. Deming et al.
IEEE Journal of Solid-State Circuits, vol. SC-19, No. 5, p. 721 (1984), "A 1K-Gate GaAs Gate Array"; Y. Ikawa et al; Oct. 1984.
Ikawa Yasuo
Kameyama Atushi
Kawakyu Katsue
Anagnos Larry N.
Kabushiki Kaisha Toshiba
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