Active solid-state devices (e.g. – transistors – solid-state diode – Heterojunction device – Between different group iv-vi or ii-vi or iii-v compounds...
Reexamination Certificate
2001-12-05
2003-12-16
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Heterojunction device
Between different group iv-vi or ii-vi or iii-v compounds...
C257S021000, C257S086000, C257S094000, C257S192000, C257S197000, C257S201000, C438S173000
Reexamination Certificate
active
06664575
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a GaInP stacked layer structure comprising a GaAs single crystal substrate having stacked on the surface thereof at least a buffer layer, an electron channel layer composed of Ga
X
In
1-X
As (0≦X≦1), a spacer layer composed of Ga
Z
In
1-Z
P (0≦Z≦1), and an electron supply layer composed of Ga
Y
In
1-Y
P (0≦Y≦1), and also relates to a field-effect transistor manufactured using the same.
BACKGROUND OF THE INVENTION
As one kind of field-effect transistors (FET) capable of operating in a millimeter wave region, a GaInP high electron mobility field-effect transistor (simply called TEFGET, MODFET or the like) using a gallium indium phosphide mixed crystal (Ga
Y
In
1-Y
P: 0≦Y≦1) is known (see, IEEE Trans. Electron Devices, Vol. 37, No. 10 (1990), pp. 2141-2147). The GaInP MODFET is being used, for example, as a low-noise signal amplification device in the microwave region (see, IEEE Trans. Electron Devices, Vol. 46, No. 1 (1999), pp. 48-54) or a high-frequency transmission device (see, IEEE Trans. Electron Devices, Vol. 44, No. 9 (1997), pp. 1341-1348).
FIG. 4
is a schematic view showing a cross-sectional structure of conventional GaInP TEGFET. For the substrate
90
, a semi-insulating gallium arsenide (chemical formula: GaAs) having a {001} crystal face as the main plane is used. On the surface of the substrate
90
, a buffer layer
91
composed of a high-resistance III-V compound semiconductor layer is deposited. On the buffer layer
91
, an electron channel layer
92
composed of an n-type gallium indium arsenide mixed crystal (Ga
X
In
1-X
As: 0≦X≦1) is deposited. On the electron channel layer
92
, a spacer layer
93
is deposited. The spacer layer
93
is generally composed of undoped Ga
Z
In
1-Z
P (0≦Z≦1) (see, IEEE Trans. Electron Devices, Vol. 44 (1997), supra). On the spacer layer
93
, an electron supply layer
94
composed of an n-type gallium indium phosphide mixed crystal (Ga
Y
In
1-Y
P: 0≦Y≦1) is deposited. The carrier (electron) concentration of the electron supply layer
94
is adjusted by intentionally adding (doping) an n-type impurity with low diffusibility, such as silicon (Si). On the electron supply layer
94
, a contact layer
95
composed of n-type GaAs or the like is generally provide for the formation of respective ohmic electrodes of low contact resistance source electrode
96
and drain electrode
97
. In the recess structure part between the source and drain electrodes
96
and
97
, a Schottky junction-type gate electrode
98
is provided on the exposed surface of the electron supply layer
94
, thereby constructing TEGFET
910
.
In the region near the junction interface
92
b
between the electron channel layer
92
and the spacer layer
93
(when a spacer layer
93
is not provided, the electron supply layer
94
), electrons fed from the electron supply layer
94
are accumulated as two-dimensional electrons. In general, as the barrier at the junction interface
92
b
between the electron channel layer
92
and the spacer layer
93
(or electron supply layer
94
) is higher, the two-dimensional electrons exerting high mobility can be more efficiently accumulated. As a usual practice, the electron channel layer
92
is composed of Ga
X
In
1-X
As having a constant composition in the thickness direction. The indium composition ratio is mainly about 0.25 (25%) at most (see, Solid-State Electron., 36 (9)(1993), pp. 1235-1237).
However, when the indium composition (=(1-X)) is set almost constant and moreover, to be about 0.25 at most, as in the above-described conventional electron channel layer
92
, the attempt to increase the height of the barrier in the vicinity of the junction interface
92
b
with the spacer layer
93
is limited. Therefore, two-dimensional electrons cannot be efficiently accumulated in the region near the junction interface
92
b
. As a result, the mobility of two-dimensional electrons cannot be enhanced and this causes a problem that a low-noise GaInP TEGFET using the mobility cannot be obtained.
Under these circumstances, the present invention has been made and an object of the present invention is to provide a GaInP stacked layer structure capable of efficiently accumulating two-dimensional electrons, thereby enhancing mobility of two-dimensional electrons, and being used as a low-noise device using the high mobility. Another object of the present invention includes providing a field-effect transistor manufactured using the GaInP stacked layer structure.
SUMMARY OF THE INVENTION
In order to attain the above-described objects, in an embodiment of the present invention, a GaInP stacked layer structure comprises a GaAs single crystal substrate having stacked on the surface thereof at least a buffer layer, an electron channel layer composed of Ga
X
In
1-X
As (0≦X≦1), a spacer layer composed of Ga
Z
In
1-Z
P (0≦Z≦1), and an electron supply layer composed of Ga
Y
In
1-Y
P (0≦Y≦1), the electron channel layer contains a compositional gradient region increased in the indium composition ratio (1-X) toward the electron supply layer side.
In a second embodiment of the present invention, in addition to the construction of the above embodiment of the present invention, the compositional gradient region is continuously or discontinuously changed in the indium composition ratio (1-X).
In a third embodiment of the present invention, in addition to the construction of the above embodiments of the present invention, the indium composition ratio (1-X) is from 0.30 to 0.50 at the junction interface in the electron supply layer side.
In a fourth embodiment of the present invention, in addition to the construction of the above embodiments of the present invention, the electron channel layer has a layer thickness of 1 to 5 nanometer.
In a fifth embodiment of the present invention, in addition to the construction of the above embodiments of the present invention, the electron channel layer is composed of n-type Ga
X
In
1-X
As (0≦X≦1) having added thereto boron (symbol of element: B).
In a sixth embodiment of the present invention of claim, in addition to the construction of the above embodiments of the present invention, the spacer layer is composed of Ga
Z
In
1-Z
P (0≦Z≦1) and contains a compositional gradient region reduced in the gallium composition ratio toward the electron supply layer side.
In a seven embodiment of the present invention, in addition to the construction of the above embodiments of the present invention, the spacer layer is not provided.
An eighth embodiment of the present invention relates to a field-effect transistor manufactured using the GaInP staked layer structure of any one of the above embodiments.
REFERENCES:
patent: 5453631 (1995-09-01), Onda et al.
patent: 6342411 (2002-01-01), Pitts, Jr.
H.M. Shieh, et al, “Improved GaAs/In0.25Ga0.75As/GaAs Pseudomorphic Heterostructure by Growing Double &dgr;-Doping GaAs Layers on Both Sides of the Channel”, Solid-State Electronics, 1993, vol. 36, No. 9, pp. 1235-1237.
Boris Pereiaslavets, et al, “Narrow-Channel GaInP/InGaAs/GaAs MODFET's for High-Frequency and Power Applications”, IEEE Transactions on Electron Devices, 1997, vol. 44, No. 9, pp. 1341-1348.
Shey-Shi Lu, et al, “The Effect of Gate Recess Profile on Device Performance of Ga0.511n0.49P/In0.2Ga0.8As Doped-Channel FET's”, IEEE Transactions on Electron Devices, 1999, vol. 46, No. 1, pp. 48-54.
Yi-Jen Chan, et al, “Ga0.51In0.49P/GaAs HEMT's Exhibiting Good Electrical Performance at Cryogenic Temperatures”, IEEE Transactions on Electron Devices, 1990, vol. 37, No. 10, pp. 2141-2147.
Showa Denko Kabushiki Kaisha
Sughrue & Mion, PLLC
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