Gain stage that minimizes the miller effect

Details Gain stage that minimizes the miller effect Gain stage that minimizes the miller effect

2002-04-22

2004-02-10

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

Nonlinear amplifying circuit

C327S562000

Reexamination Certificate

active

06690231

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to active devices which are utilized to provide a gain and more particularly to a system and method for minimizing the Miller Effect in such devices.
BACKGROUND OF THE INVENTION
FIG. 1
illustrates a typical active device
10
(i.e., a transistor) which includes a Miller feedback capacitance
12
. In any three-terminal active device, there exists a feedback (Miller) capacitance between the input and output terminals as shown in
FIG. 1
, which causes gain reduction and degrades isolation and stability of the device in high frequencies. That phenomenon is commonly known as Miller Effect.
FIG. 2
illustrates a simple circuit
20
model illustrating the active device when determining the figure of merit (f
T
). The circuit
20
includes an input resistance (R
m
)
22
coupled in parallel to an input capacitor (C
in
)
24
. The parallel resistor/capacitor combination is coupled to a current source
26
. The current gain (Beta) for such a device is defined by Iin/Iout.
The parameter called f
T
defines the figure of merit for any technology, which is the ratio of transconductance and input capacitance of a three terminal device such as the transistor
10
. As is well known, at high frequencies f is defined by the following equation:
f
T
=gm/(2*II*
C
in
), where gm=the gain.  (1)
It is well known that f
T
is a good measure of the performance of a device based upon process parameters. However, circuit performance of the device must also be determined. Measurement of circuit performance of a device is accomplished by placing a load on the output of the device.
FIG. 3
illustrates a circuit model
30
which includes a load resistance (RL)
32
and the Miller Effect capacitance C
m
31
. The figure of merit for device performance is the maximum oscillation frequency (f
max
). The Miller Effect capacitance is a limitation to any device technology. Despite progress made in each successive generation of technology that pushes the speed higher and higher, Miller Effect capacitance always becomes a limiting factor in high-frequency operation of such devices. For a more specific description of this problem, refer now to the following discussion.
F
max
is related to the f
T
approximately by the following equation:
f
max
≈{square root over ((
fr
/(8
*&pgr;*R
Series
*C
Feedback
)))}  (2)
where R
Series
is the series resistance at the input terminal.
As a rule of thumb, high-frequency gain rolls off at 6 dB per octave. And when it reaches 0 dB, that frequency is called f
Max
. The circuit should operate at frequencies much below the f
Max
to have meaningful gain. Unfortunately, the f
Max
also is a fixed parameter for a given technology.
So at high frequencies the limitation is accepted as is or a cascode stage or neutralization is provided for better performance. Both of these alternatives have limitations, however. For a description of these two alternatives, refer now to the following discussion
FIG. 4
illustrates a typical cascode stage configuration
50
. The cascode stage configuration
50
feeds the output of a first device
52
into the emitter (or the source, if it is a FET) of a second device
54
. It is known that the Miller Effect capacitance will manifest the total capacitance at the input by:
C
Total
=(1
−K
)*
C
Feedback
+C
in
,
where K is the voltage gain between the output and input. In an ideal cascode stage K=−1.
Accordingly, the gain for the output can be held stable under most conditions. However, the cascode stage configuration
50
has several problems. Firstly, the gain of the lower device is maximized at 1. Hence, the distortion voltage doubles as both upper and lower devices make equal contributions in distortion from same voltage swing simultaneously.
Secondly, at low voltages (i.e., 3.3 Volts or less), headroom of voltage for operation is limited due to the voltage drops required across both of the transistors.
The second approach is referred to as a neutralization technique.
FIG. 5
illustrates a typical single device stage
60
with neutralization. In this technique, a capacitance is introduced to provide a positive feedback via a unity-gain phase inverter
66
to cancel the negative feedback from Miller Effect capacitor
62
. This technique has been applied to vacuum tube, bipolar and FET stages.
However, the neutralization technique is based on the assumption that the added capacitance will match the feedback capacitance exactly. Whether it is from part to part, from temperature to temperature, or from frequency to frequency. Finally, the neutralization technique requires the phase inverter to provide unity gain. Skillful designers know those conditions are impossible to meet in production.
So for circuits utilizing a neutralization technique, manual tuning is a necessity in production. It also means risk of oscillation, as exact neutralization is not guaranteed over the temperature and frequency.
Accordingly, what is needed is a system and method for providing an active device where the Miller Effect capacitance is minimized which overcomes the above-identified problems. The device should be cost effective, compatible with existing processes and easily implemented. The present invention addresses such a need.
SUMMARY OF THE INVENTION
A gain stage is disclosed. The gain stage comprises a first stage that provides two voltages of equal and opposites polarities and a plurality of devices cross coupled to the first stage. The plurality of devices minimize the Miller Effect capacitance in the differential stage by providing an out-of-phase signal to the first stage
Accordingly, a system and method in accordance with the present invention utilizes at least one device on the same die as the first stage to provide an impedance match. In so doing, a broadband cancellation of the Miller Effect is achieved. Moreover, the matching is valid over an extended temperature range.


REFERENCES:
patent: 4132963 (1979-01-01), Page
patent: 4656436 (1987-04-01), Saari
patent: 5430641 (1995-07-01), Kates
patent: 5491641 (1996-02-01), Scepanovic et al.
patent: 6107885 (2000-08-01), Miguelez et al.
patent: 11088064 (1999-03-01), None

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