Gain linearity correction for MOS circuits

Details Gain linearity correction for MOS circuits Gain linearity correction for MOS circuits

1993-08-23

1994-07-19

Zazworsky, John

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

3072968, 307304, 307307, 307568, H03K 1714, H03K 3013, H03F 130

Patent

active

053312210

ABSTRACT:
Gain linearity problems caused by impact ionization in a active MOS device are avoided by connecting an MOS shield device in series with the active MOS device so that the overall supply voltage is split across two devices, keeping both devices in a region of operation well below where impact ionization becomes a significant problem. The gate of the MOS shield device is maintained at a voltage proportional to its drain voltage, thereby keeping the device in the saturation mode and avoiding an abrupt mode change associated with prior art shield circuits.

REFERENCES:
patent: 4717846 (1988-01-01), Ando
patent: 4740713 (1988-04-01), Sakurai et al.
patent: 4920287 (1990-04-01), Hartgring et el.
patent: 4996446 (1991-02-01), Nakada
Design Considerations for a High-Performance Three Micrometer CMOS Analog Standard-Cell Library, C. A. Laber et al.
U. Gatti et al.: "A Novel CMOS Linear Transconductance Cell for Continuous-Time Filters".

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