Gain linearity correction circuit for MOS circuits

Details Gain linearity correction circuit for MOS circuits Gain linearity correction circuit for MOS circuits

1994-06-15

1996-05-14

Tran, Toan

Miscellaneous active electrical nonlinear devices, circuits, and

Specific input to output function

Having feedback

327328, 327581, G06G 712, H03K 1714

Patent

active

055171494

ABSTRACT:
Gain linearity problems caused by impact ionization in a active MOS device are avoided by connecting an MOS shield device in series with the active MOS device so that the overall supply voltage is split across two devices, keeping both devices in a region of operation well below where impact ionization becomes a significant problem. The gate of the MOS shield device is maintained at a voltage proportional to its drain voltage, thereby keeping the device in the saturation mode and avoiding an abrupt mode change associated with prior art shield circuits.

REFERENCES:
patent: 4647872 (1987-03-01), Johnson
patent: 4717846 (1988-01-01), Ando
patent: 4740713 (1988-04-01), Sakurai et al.
patent: 4920287 (1990-04-01), Hartgring et al.
patent: 4996446 (1991-02-01), Nakada
Gatti et al., "A Novel CMOS Linear Transconductance Cell For Continuous-Time Filters", IEEE, 1990, pp. 1173-1176.
Laber et al., "Design Considerations for a High Performance 3-.mu.m CMOS Analog Standard-Cell Library", 1987 IEEE, pp. 181-189.

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